LM3S1512 Luminary Micro, Inc, LM3S1512 Datasheet - Page 466

• Manufacturer Part Number: LM3S1512
• Description: Lm3s1512 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Signal Tables
466
General-Purpose
Timers
I2C
JTAG/SWD/SWO
Power
Function
CCP0
CCP1
CCP2
CCP3
CCP4
CCP5
CCP6
CCP7
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SWCLK
SWDIO
SWO
TCK
TDI
TDO
TMS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDA
GNDA
HIB
LDO
Pin Name
Number
D12
C12
M12
E12
C11
A10
A10
L10
K10
F10
F12
Pin
J10
F11
M6
E1
E2
C9
C8
A9
B9
A9
B8
B9
C4
C5
H3
K5
K6
B6
B5
A5
E3
F1
L1
L6
J3
Preliminary
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
I
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Buffer
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
OD
OD
OD
OD
Capture/Compare/PWM 0
Capture/Compare/PWM 1
Capture/Compare/PWM 2
Capture/Compare/PWM 3
Capture/Compare/PWM 4
Capture/Compare/PWM 5
Capture/Compare/PWM 6
Capture/Compare/PWM 7
I2C module 0 clock
I2C module 0 data
I2C module 1 clock
I2C module 1 data
JTAG/SWD CLK
JTAG TMS and SWDIO
JTAG TDO and SWO
JTAG/SWD CLK
JTAG TDI
JTAG TDO and SWO
JTAG TMS and SWDIO
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
The ground reference for the analog circuits (ADC,
Analog Comparators, etc.). These are separated
from GND to minimize the electrical noise contained
on VDD from affecting the analog functions.
An output that indicates the processor is in
hibernate mode.
Low drop-out regulator output voltage. This pin
requires an external capacitor between the pin and
GND of 1 µF or greater. The LDO pin must also be
Description
July 25, 2008