LM3S1332 Luminary Micro, Inc, LM3S1332 Datasheet - Page 408

• Manufacturer Part Number: LM3S1332
• Description: Lm3s1332 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Signal Tables
408
SSI
System Control &
Clocks
Function
VBAT
VDD25
VDD25
VDD25
VDD25
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDDA
VDDA
WAKE
SSI0Clk
SSI0Fss
SSI0Rx
SSI0Tx
CMOD0
CMOD1
OSC0
OSC1
RST
TRST
XOSC0
Pin Name
Number
G12
H10
G10
M10
M11
L12
E10
G11
E11
B10
H11
K11
Pin
L11
M4
M5
C3
D3
G3
K7
K8
K9
C6
C7
A8
F3
L4
L5
Preliminary
Pin Type
I/O
I/O
I/O
I/O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
I
Analog
Analog
Analog
Buffer
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
-
Power source for the Hibernation Module. It is
normally connected to the positive terminal of a
battery and serves as the battery
backup/Hibernation Module power-source supply.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for most of the logic function,
including the processor core and most peripherals.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
Positive supply for I/O and some logic.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
The positive supply (3.3 V) for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from VDD to minimize the electrical noise
contained on VDD from affecting the analog
functions.
An external input that brings the processor out of
hibernate mode when asserted.
SSI module 0 clock
SSI module 0 frame
SSI module 0 receive
SSI module 0 transmit
CPU Mode bit 0. Input must be set to logic 0
(grounded); other encodings reserved.
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
Main oscillator crystal input or an external clock
reference input.
Main oscillator crystal output.
System reset input.
JTAG TRSTn
Hibernation Module oscillator crystal input or an
external clock reference input. Note that this is
either a 4.19-MHz crystal or a 32.768-kHz oscillator
Description
July 26, 2008