LM3S1332 Luminary Micro, Inc, LM3S1332 Datasheet - Page 351
![no-image](/images/no-image-200.jpg)
LM3S1332
Manufacturer Part Number
LM3S1332
Description
Lm3s1332 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1332.pdf
(447 pages)
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Reset
Reset
Type
Type
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
July 26, 2008
Bit/Field
31:5
4
3
2
1
RO
RO
31
15
0
0
Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
RO
RO
30
14
0
0
reserved
RO
RO
29
13
0
0
Name
RNE
BSY
RFF
TNF
RO
RO
28
12
0
0
RO
RO
27
11
0
0
Type
RO
RO
RO
RO
RO
reserved
RO
RO
26
10
0
0
Reset
0x00
RO
RO
25
0
9
0
0
0
0
1
Preliminary
RO
RO
24
0
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
SSI Busy Bit
The BSY values are defined as follows:
SSI Receive FIFO Full
The RFF values are defined as follows:
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
Value
Value
Value
Value
reserved
0
1
0
1
0
1
0
1
RO
RO
23
Description
SSI is idle.
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
Description
Receive FIFO is not full.
Receive FIFO is full.
Description
Receive FIFO is empty.
Receive FIFO is not empty.
Description
Transmit FIFO is full.
Transmit FIFO is not full.
0
7
0
RO
RO
22
0
6
0
RO
RO
21
0
5
0
BSY
RO
RO
20
0
4
0
LM3S1332 Microcontroller
RFF
RO
RO
19
0
3
0
RNE
RO
RO
18
0
2
0
TNF
RO
RO
17
0
1
1
TFE
RO
R0
16
0
0
1
351
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