SN74LS75 Motorola, SN74LS75 Datasheet
SN74LS75
Manufacturer Part Number
SN74LS75
Description
4-BIT D LATCH LOW POWER SCHOTTKY
Manufacturer
Motorola
Datasheet
1.SN74LS75.pdf
(4 pages)
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4-BIT D LATCH
porary storage for binary information between processing units and input /out-
put or indicator units. Information present at a data (D) input is transferred to
the Q output when the Enable is HIGH and the Q output will follow the data
input as long as the Enable remains HIGH. When the Enable goes LOW, the
information (that was present at the data input at the time the transition oc-
curred) is retained at the Q output until the Enable is permitted to go HIGH.
latch and is available in the 16-pin packages. For higher component density
applications the SN54 / 74LS77 4-bit latch is available in the 14-pin package
with Q outputs omitted.
NOTES:
a) 1 Unit Load (U.L.) = 40 A HIGH.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
PIN NAMES
D 1 –D 4
E 0–1
E 2–3
Q 1 –Q 4
Q 1 –Q 4
Temperature Ranges.
The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as tem-
The SN54 / 74LS75 features complementary Q and Q output from a 4-bit
CONNECTION DIAGRAMS DIP (TOP VIEW)
TRUTH TABLE
t n
D
H
L
Data Inputs
Enable Input Latches 0, 1
Enable Input Latches 2, 3
Latch Outputs (Note b)
Complimentary Latch Outputs (Note b)
Q 0
Q 0
16
(Each latch)
1
Q 0
D 0
14
1
Q 1
D 0
15
2
Q 1
D 1
13
2
t n + 1
Q
H
Q 1
D 1
L
14
3
SN54 / 74LS77
SN54 / 74LS75
E 2–3
E 0–1 GND
12
3
E 0–1 GND
E 2–3 V CC
13
4
V CC
11
4
12
5
NOTES:
t n = bit time before enable
negative-going transition
t n+1 = bit time after enable
negative-going transition
NC
D 2
10
5
Q 2
D 2
11
6
Q 2
D 3
9
6
FAST AND LS TTL DATA
Q 2
10
D 3
7
Q 3
NC
8
7
0.5 U.L.
2.0 U.L.
2.0 U.L.
HIGH
10 U.L.
10 U.L.
LOADING (Note a)
Q 3
Q 3
9
8
5-1
5 (2.5) U.L.
5 (2.5) U.L.
0.25 U.L.
LOW
1.0 U.L.
1.0 U.L.
14
16
14
16
14
ORDERING INFORMATION
SN54/74LS75
SN54/74LS77
16
1
LOW POWER SCHOTTKY
1
1
1
SN54LSXXJ
SN74LSXXN
SN74LSXXD
1
1
4-BIT D LATCH
Ceramic
Plastic
SOIC
CASE 751A-02
CASE 751B-03
CASE 632-08
CASE 646-06
CASE 620-09
CASE 648-08
CERAMIC
CERAMIC
N SUFFIX
D SUFFIX
N SUFFIX
D SUFFIX
J SUFFIX
J SUFFIX
PLASTIC
PLASTIC
SOIC
SOIC
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SN74LS75 Summary of contents
Page 1
D LATCH The TTL/MSI SN54 / 74LS75 and SN54 / 74LS77 are latches used as tem- porary storage for binary information between processing units and input /out- put or indicator units. Information present at a data (D) input is ...
Page 2
SN54/74LS75 0– PIN 5 E 2–3 4 GND = PIN ...
Page 3
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE Symbol Parameter V IH Input HIGH Voltage Input LOW Voltage Input LOW Voltage V IK Input Clamp Diode Voltage Output HIGH Voltage ...
Page 4
SN54/74LS75 DATA ENABLE TO OTHER LATCH GUARANTEED OPERATING RANGES Symbol Parameter V CC Supply Voltage T A Operating Ambient Temperature Range I OH Output Current — High I OL Output Current — Low AC SETUP REQUIREMENTS ( ...