ADP3211 ON Semiconductor, ADP3211 Datasheet - Page 25

• Manufacturer Part Number: ADP3211
• Description: 7-bit, Programmable, Single-phase, Synchronous Buck Controller
• Manufacturer: ON Semiconductor

transient response, the ESR of the bulk capacitor bank (R
should be less than two times the droop resistance, R
the C
meet the VID OTF specifications and may require less
inductance. In addition, the switching frequency may have
to be increased to maintain the output ripple.
capacitors (C
change, the V
setting error of 10 mV. If k = 3.1, solving for the bulk
capacitance yields:
C
C
+ 992 mF
ESR of 7 mW each yields C
enough to limit the high frequency ringing during a load
change. This is tested using:
where:
Q is limited to the square root of 2 to ensure a critically
damped system.
L
enough to avoid ringing during a load change. If the L
the chosen bulk capacitor bank is too large, the number of
ceramic capacitors may need to be increased to prevent
excessive ringing.
X
X(MIN)
X(MAX)
To meet the conditions of these expressions and the
For example, if two pieces of 22 mF, 0805−size MLC
Using two 220 mF Panasonic SP capacitors with a typical
Ensure that the ESL of the bulk capacitors (L
is about 450 pH for the two SP capacitors, which is low
1)
X(MIN)
L
L
X
X
w
v
v C
v 44 mF
22 ms
3.1
is greater than C
5.1 mW)
Z
Z
2
CCGFX
= 44 mF) are used during a VID voltage
560 nH
220 mV
R
(5.1 mW)
1.174 V
O
560 nH
(5.1 mW)
2
change is 220 mV in 22 ms with a
10 mV
8 A
Q
220 mV
2
2
X
560 nH
2
3.1
X(MAX)
8 A
= 440 mF and R
1.174 V
1.174 V
2 + 2.3 nH
C
C
5.1 mW
X(MIN)
X(MAX)
, the system does not
−44 mF + 256 mF
where k + −1n
w
v
2
k
−1 −44 mF
X
2
R
= 3.5 mW.
X
O
L
) is low
(eq. 18)
R
)
(eq. 17)
http://onsemi.com
o
2
O
V
X
L
. If
OSMAX
X
DI
of
)
V
O
V
V
DI
VID
V
ERR
25
V
O
V
capacitor design can be used if the conditions of
Equations 15, 16, and 18 are satisfied.
Power MOSFETs
MOSFETs are selected for one high−side switch and two
low−side switch. The main selection parameters for the
power MOSFETs are V
R
logic−level threshold MOSFETs must be used.
R
MOSFETs. With conduction losses being dominant, the
following expression shows the total power that is
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (I
current (I
P
where:
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
I
approximately:
allowed power dissipation, the user can calculate the
required R
8−lead SOIC−compatible MOSFET, the junction to
ambient (PCB) thermal impedance is 50°C/W. In the worst
case, the PCB temperature is 70°C to 80°C during heavy
load operation of the notebook, and a safe limit for P
about 0.8 W to 1.0 W at 120°C junction temperature.
Therefore, for this example (15 A maximum), the R
per MOSFET is less than 18.8 mW for the low−side
MOSFET. This R
R
DS(ON)
DS(ON)
SF
V
For this multi−mode control technique, an all ceramic
For typical 15 A applications, the N−channel power
The maximum output current, I
Knowing the maximum output current and the maximum
VID
is the inductor peak−to−peak ripple current and is
+ (1 * D)
1 ) t
* C
. Because the voltage of the gate driver is 5.0 V,
O
requirement for the low−side (synchronous)
DS(ON)
):
Z
v
V
V
VID
V
DS(SF)
for the MOSFET. For an 8−lead SOIC or
I
R
+
n
k
I
O
SF
(1 * D)
is also at a junction temperature of
L
R
GS(TH)
R
2
L
o
) and the average total output
) 1
2
12
* 1 * C
f
, Q
SW
V
OUT
G
n
, C
O
I
SF
R
, determines the
Z
ISS
2
, C
RSS
R
(eq. 15)
(eq. 16)
(eq. 19)
DS(SF)
(eq. 20)
DS(SF)
, and
SF
is