AD8197A-EVALZ Analog Devices, AD8197A-EVALZ Datasheet - Page 26

• Manufacturer Part Number: AD8197A-EVALZ
• Description: 4:1 HDMI/DVI Switch with Equalization; Package: EVALUATION BOARDS; No of Pins: -; Temperature Range: Industrial
• Manufacturer: Analog Devices

AD8197A
AD8197A and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8197A is being used.
For example, the maximum speed of signals present on the
auxiliary lines is 100 kHz I
any layout that enables 100 kHz I
bus should suffice. The HDMI 1.3 specification, however, places
a strict 50 pF limit on the amount of capacitance that can be
measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8197A, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stackup, relieving or clearing out this reference plane
directly under the auxiliary traces significantly decreases the
amount of parasitic trace capacitance. An example of the board
stackup is shown in Figure 33.
SILKSCREEN
LAYER 1: SIGNAL (MICROSTRIP)
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 3: PWR (REFERENCE PLANE)
PCB DIELECTRIC
LAYER 4: SIGNAL (MICROSTRIP)
SILKSCREEN
Figure 33. Example Board Stackup
2
C data on the DDC lines; therefore,
2
C to be passed over the DDC
3W
RELIEVED UNDERNEATH
REFERENCE LAYER
MICROSTRIP
W
3W
Rev. 0 | Page 26 of 28
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement
of this signal is not critical, but it should be routed as directly
as possible.
When the AD8197A is powered up, one set of the auxiliary in-
puts is passively routed to the outputs. In this state, the
AD8197A looks like a 100 Ω resistor between the selected
auxiliary inputs and the corresponding outputs as illustrated in
Figure 27. The AD8197A does not buffer the auxiliary signals,
therefore, the input traces, output traces, and the connection
through the AD8197A all must be considered when designing a
PCB to meet HDMI/DVI specifications. The unselected auxiliary
inputs of the AD8197A are placed into a high impedance mode
when the device is powered up. To ensure that all of the
auxiliary inputs of the AD8197A are in a high impedance mode
when the device is powered off, it is necessary to power the
AMUXVCC supply as illustrated in Figure 28.
In contrast to the auxiliary signals, the AD8197A buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.
Power Supplies
The AD8197A has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are:
•
•
•
•
•
The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies
power the core of the AD8197A. The VTTI/AVEE supply
(3.3 V) powers the input termination (see Figure 25). Similarly,
the VTTO/AVEE supply (3.3 V) powers the output termination
(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)
powers the auxiliary multiplexer core and determines the
maximum allowed voltage on the auxiliary lines. For example,
if the DDC bus is using 5 V I
connected to 5 V relative to DVEE.
In a typical application, all pins labeled AVEE or DVEE should
be connected directly to ground. All pins labeled AVCC,
DVCC, VTTI, or VTTO should be connected to 3.3 V, and
Pin AMUXVCC tied to 5 V. The supplies can also be powered
individually, but care must be taken to ensure that each stage of
the AD8197A is powered correctly.
AVCC/AVEE
VTTI/AVEE
VTTO/AVEE
DVCC/DVEE
AMUXVCC/DVEE
2
C, AMUXVCC should be