AD8197A-EVALZ Analog Devices, AD8197A-EVALZ Datasheet
AD8197A-EVALZ
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AD8197A-EVALZ Summary of contents
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... Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. The AD8197A is provided in a 100-lead LQFP, Pb-free, surface- mount package, specified to operate over the −40°C to +85°C temperature range. ...
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... AD8197A TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Typical Application........................................................................... 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 Maximum Power Dissipation ..................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 9 Eye Diagrams ................................................................................ 9 Performance Graphs .................................................................. 11 Theory of Operation ...................................................................... 13 Introduction ...
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... Outputs enabled, maximum pre-emphasis 4 Input termination on Output termination on, no pre-emphasis Output termination on, maximum pre-emphasis Outputs disabled Outputs enabled, no pre-emphasis Outputs enabled, maximum pre-emphasis High speed switching register: HS_CH All other configuration registers Rev Page AD8197A Min Typ Max Unit 2.25 Gbps − (p-p) ...
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... Differential interpair skew is measured between the TMDS pairs of a single link. 2 AD8197A output meets the transmitter eye diagram as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. 3 Cable output meets the receiver eye diagram mask as defined in the DVI Standard Revision 1.0 and the HDMI Standard Revision 1.3. ...
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... Package Type 100-Lead LQFP MAXIMUM POWER DISSIPATION < AVCC + 0 The maximum power that can be safely dissipated by the AD8197A is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated < AMUXVCC + 0 devices is determined by the glass transition temperature of the < ...
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... IP_B3 14 IN_A0 15 IP_A0 17 IN_A1 18 IP_A1 20 IN_A2 21 IP_A2 23 IN_A3 AD8197A TOP VIEW (Not to Scale) Figure 3. Pin Configuration 1 Type Description Power Positive Analog Supply. 3.3 V nominal High Speed Input Complement High Speed Input. Power Negative Analog Supply nominal High Speed Input Complement. ...
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... Low Speed Input/Output. LS I/O Low Speed Input/Output. Power Positive Auxiliary Multiplexer Supply typical. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. LS I/O Low Speed Common Input/Output. Rev Page AD8197A ...
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... AD8197A Pin No. Mnemonic 90 AUX_COM0 91 AUX_B3 92 AUX_B2 93 AUX_B1 94 AUX_B0 96 AUX_A3 97 AUX_A2 98 AUX_A1 99 AUX_A0 100 PP_OTO high speed low speed input output. 1 Type Description LS I/O Low Speed Common Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. LS I/O Low Speed Input/Output. ...
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... Figure 7. Rx Eye Diagram at TP3 (Cable = 2 meters, 30 AWG) Figure 8. Rx Eye Diagram at TP3 (Cable = 20 meters, 24 AWG) Rev Page − 1, data rate = 2.25 Gbps, unless AD8197A SERIAL DATA EVALUATION ANALYZER BOARD SMA COAX CABLE TP2 TP3 0.125UI/DIV AT 2.25Gbps 0.125UI/DIV AT 2.25Gbps AD8197A ...
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... AD8197A REFERENCE EYE DIAGRAM AT TP1 0.125UI/DIV AT 2.25Gbps Figure 10. Tx Eye Diagram at TP2 0.125UI/DIV AT 2.25Gbps Figure 11. Tx Eye Diagram at TP2 AD8197A DIGITAL EVALUATION PATTERN BOARD GENERATOR SMA COAX CABLE TP1 TP2 Figure 9. Test Circuit Diagram for Tx Eye Diagrams Figure 12. Tx Eye Diagram at TP3 (Cable = 2 meters, 30 AWG) Figure 13 ...
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... PE OFF 2.25Gbps, PE MAX 0.2 0.1 1.65Gbps, PE MAX HDMI CABLE LENGTH (m) 1200 1000 800 600 400 200 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 DATA RATE (Gbps) Figure 18. Eye Height vs. Data Rate 800 700 600 500 400 300 200 100 0 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 SUPPLY VOLTAGE (V) Figure 19. Eye Height vs. Supply Voltage AD8197A 20 2.0 2.2 2.4 3.4 3.5 3.6 ...
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... AD8197A (p- (rms 0.2 0.4 0.6 0.8 1.0 1.2 DIFFERENTIAL INPUT SWING (V) Figure 20. Jitter vs. Differential Input Swing (p- (rms) 0 –40 – TEMPERATURE (°C) Figure 21. Jitter vs. Temperature 160 140 FALL TIME 120 RISE TIME 100 –40 –20 ...
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... I C slave addresses to allow multiple AD8197A devices to be controlled by a single I pin is provided to restore the control registers of the AD8197A to default values. In all cases, serial programming values override any prior parallel programming values and any use of the serial control interface disables the parallel control interface until the AD8197A is reset ...
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... EDID devices may need to be available via the DDC bus, regardless of the state of the AD8197A and any downstream circuit. For this configuration, the auxiliary inputs of the powered down AD8197A need high impedance state to avoid pulling down on the DDC lines and preventing these other devices from using the bus. ...
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... I2C_SDA line low). 2. Send the AD8197A part address (seven bits). The upper four bits of the AD8197A part address are the static value [1001] and the three LSBs are set by Input Pin I2C_ADDR2, Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB). ...
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... Pin I2C_ADDR0 (LSB). This transfer should be MSB first. 9. Send the read indicator bit (1). 10. Wait for the AD8197A to acknowledge the request. 11. The AD8197A serially transfers the data (eight bits) held in the register indicated by the address set in Step 5. This data is sent MSB first. 12. Acknowledge the data from the AD8197A. ...
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... Table 1. Setting these pins updates the parallel control interface registers, as listed in Table 18. Following a reset, the AD8197A can be controlled through the parallel control interface until the first serial control event occurs. As soon as any serial control ...
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... The serial interface configuration registers can be read and written using the I The least significant bits of the AD8197A I 3.3 V (Logic (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8197A is reset, as described in the Serial Control Interface section. ...
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... RX_PT[x] Corresponding Input TMDS Channel Bit 0 B0 Bit 1 B1 Bit 2 B2 Bit 3 B3 Bit 4 A0 Bit 5 A1 Bit 6 A2 Bit 7 A3 Bit 8 C3 Bit 9 C2 Bit 10 C1 Bit 11 C0 Bit 12 D3 Bit 13 D2 Bit 14 D1 Bit 15 D0 Rev Page AD8197A ...
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... AD8197A RECEIVE EQUALIZER REGISTER 1 AND REGISTER 2 RX_EQ[x]: High Speed (TMDS) Input X Equalization Level Select Bit Table 13. RX_EQ[x] Description RX_EQ[x] Description 0 Low equalization (6 dB) 1 High equalization (12 dB) Table 14. RX_EQ[x] Mapping RX_EQ[x] Corresponding Input TMDS Channel Bit 0 B0 Bit 1 B1 Bit 2 B2 Bit 3 ...
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... High speed source select 0 PP_CH[1] PP_CH[0] Auxiliary switch source select 0 PP_CH[1] PP_CH[0] Input termination on/off select (termination always on PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ PP_EQ High speed High speed output output current level select termination on/off select PP_PE[0] PP_OTO PP_OCL AD8197A ...
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... AD8197A HIGH SPEED DEVICE MODES REGISTER PP_EN: High Speed (TMDS) Channel Enable Bit Table 19. PP_EN Description PP_EN Description 0 High speed channels off, low power/standby mode 1 High speed channels on PP_CH[1:0]: High Speed (TMDS) Switch Source Select Bus Table 20. High Speed Switch Mapping ...
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... APPLICATION INFORMATION Figure 31. Layout of the TMDS Traces on the AD8197A Evaluation Board (Only Top Signal Routing Layer is Shown) The AD8197A is an HDMI/DVI switch, featuring equalized TMDS inputs and pre-emphasized TMDS outputs in- tended for use as a 4:1 switch in systems with long cable runs on both the input and/or the output, and is fully HDMI 1 ...
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... TMDS traces is more sensitive to the PCB layout. Regardless of the data being carried on a specific TMDS channel, or whether the TMDS line is at the input or the output of the AD8197A, all four high speed signals should be routed on a PCB in accor- dance with the same RF layout guidelines. ...
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... Ground Current Return In some applications, it can be necessary to invert the output pin order of the AD8197A. This requires a designer to route the TMDS traces on multiple layers of the PCB. When routing differential pairs on multiple layers also necessary to reroute the corresponding reference plane to provide one continuous ground current return path for the differential signals ...
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... EDID is available for reading. The placement of this signal is not critical, but it should be routed as directly as possible. When the AD8197A is powered up, one set of the auxiliary in- puts is passively routed to the outputs. In this state, the AD8197A looks like a 100 Ω resistor between the selected auxiliary inputs and the corresponding outputs as illustrated in Figure 27 ...
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... RECOMMENDED NOT RECOMMENDED Figure 34. Recommended Pad Outline for Bypass Capacitors In applications where the AD8197A is powered by a single 3.3 V supply recommended to use two reference supply planes and bypass the 3.3 V reference plane to the ground reference plane with one 220 pF capacitor, one 1000 pF capacitor, two 0.01 μ ...
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... Model Temperature Range 1 AD8197AASTZ −40°C to +85°C 1 AD8197AASTZ-RL −40°C to +85°C AD8197A-EVALZ RoHS Compliant Part. Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I © ...