XC3S1200E-5FT256C Xilinx, Inc., XC3S1200E-5FT256C Datasheet - Page 36
XC3S1200E-5FT256C
Manufacturer Part Number
XC3S1200E-5FT256C
Description
XC3S1200E-5FT256C
Manufacturer
Xilinx, Inc.
Datasheet
1.XC3S1200E-5FT256C.pdf
(233 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 36 of 233
- Download datasheet (4Mb)
Functional Description
Table 22: Port Aspect Ratios
If the data bus width of Port A differs from that of Port B, the
block RAM automatically performs a bus-matching function
as described in
with a narrow bus and then read from a port with a wide bus,
the latter port effectively combines “narrow” words to form
“wide” words. Similarly, when data is written into a port with
a wide bus and then read from a port with a narrow bus, the
latter port divides “wide” words to form “narrow” words. Par-
36
Notes:
1.
2.
3.
4.
Path Width
Total Data
(w bits)
The width of the total data path (w) is the sum of the DI/DO bus width (w-p) and any parity bits (p).
The width selection made for the DI/DO bus determines the number of address lines (r) according to the relationship expressed as:
r = 14 – [log(w–p)/log(2)].
The number of address lines delimits the total number (n) of addressable locations or depth according to the following equation: n = 2
The product of w and n yields the total block RAM capacity.
18
36
1
2
4
9
DI/DO Data
Bus Width
(w-p bits)
Figure
16
32
1
2
4
8
31. When data is written to a port
1
Parity Bus
DIP/DOP
(p bits)
Width
0
0
0
1
2
4
(r bits)
ADDR
Width
Bus
14
13
12
11
10
9
2
www.xilinx.com
[w-p-1:0]
DI/DO
[15:0]
[31:0]
[0:0]
[1:0]
[3:0]
[7:0]
ity bits are not available if the data port width is configured
as x4, x2, or x1. For example, if a x36 data word (32 data, 4
parity) is addressed as two x18 halfwords (16 data, 2 par-
ity), the parity bits associated with each data byte are
mapped within the block RAM to the appropriate parity bits.
The same effect happens when the x36 data word is
mapped as four x9 words.
DIP/DOP
[p-1:0]
[0:0]
[1:0]
[3:0]
-
-
-
ADDR
[r-1:0]
[13:0]
[12:0]
[11:0]
[10:0]
[9:0]
[8:0]
Locations (n)
Addressable
DS312-2 (v3.8) August 26, 2009
16,384
No. of
8,192
4,096
2,048
1,024
512
Product Specification
3
Block RAM
(w*n bits)
Capacity
16,384
16,384
16,384
18,432
18,432
18,432
r
.
4
R
Related parts for XC3S1200E-5FT256C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
1000000 SYSTEM GATE 1.2 VOLT FPGA
Manufacturer:
Xilinx, Inc.
Datasheet:
Part Number:
Description:
Spartan-3E FPGA Family
Manufacturer:
Xilinx, Inc.
Datasheet:
Part Number:
Description:
XC95144 In-System Programmable CPLD
Manufacturer:
Xilinx, Inc.
Part Number:
Description:
XC95144 In-System Programmable CPLD
Manufacturer:
Xilinx, Inc.
Part Number:
Description:
XC95144XL High Performance CPLD
Manufacturer:
Xilinx, Inc.
Part Number:
Description:
High-performance CPLD. Speed 5ns pin-to-pin delay.
Manufacturer:
Xilinx, Inc.
Part Number:
Description:
High-performance CPLD. Speed 10ns pin-to-pin delay.
Manufacturer:
Xilinx, Inc.
Part Number:
Description:
128 MACROCELL 1.8V ZERO POWER ISP CPLD
Manufacturer:
Xilinx, Inc.
Part Number:
Description:
CPLD, CoolRunner-II Family, CMOS Process, 256 Macro Cells, 256 Reg., 106 User I/Os, 1.8V Supply, 5 Speed Grade, 132BGA
Manufacturer:
Xilinx, Inc.