MCP40D17 Microchip Technology Inc., MCP40D17 Datasheet - Page 10

no-image

MCP40D17

Manufacturer Part Number
MCP40D17
Description
7-bit Single I 2 C? With Command Code Digital Pot With Volatile Memory In Sc70
Manufacturer
Microchip Technology Inc.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCP40D17T-103E/LT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
MCP40D17T-104E/LT
Manufacturer:
BROADCOM
Quantity:
210
Part Number:
MCP40D17T-104E/LT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
MCP40D17T-502E/LT
Manufacturer:
ADI
Quantity:
88
Part Number:
MCP40D17T-502E/LT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
MCP40D17T-503E/LT
Manufacturer:
Microchip
Quantity:
5 397
Part Number:
MCP40D17T-503E/LT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
MCP40D17/18/19
TABLE 1-2:
DS22152B-page 10
I
Note 1:
Parame-
102A
102B
103A
103B
2
ter No.
C AC Characteristics
100
101
106
107
109
110
( 5)
( 5)
( 5)
( 5)
2:
3:
4:
5:
6:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
A fast-mode (400 kHz) I
requirement tsu; DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
T
the SCL line is released.
The MCP40D18/MCP40D19 device must provide a data hold time to bridge the undefined part between
V
must be tested in order to guarantee that the output data will meet the setup and hold specifications for the
receiving device.
Use C
Not Tested.
A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
T
T
R
IH
T
T
T
T
T
T
HD
SU
T
Sym
RSDA
T
T
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
RSCL
FSDA
HIGH
FSCL
LOW
and V
BUF
AA
SP
:
:
DAT
DAT
b
I
2
in pF for the calculations.
C BUS DATA REQUIREMENTS (SLAVE MODE)
IL
Characteristic
Clock high time
Clock low time
SCL rise time
SDA rise time
SCL fall time
SDA fall time
Data input hold
time
Data input
setup time
Output valid
from clock
Bus free time
Input filter spike
suppression
(SDA and SCL)
of the falling edge of the SCL signal. This specification is not a part of the I
2
C-bus device can be used in a standard-mode (100 kHz) I
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
Operating Voltage V
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
DD
4000
4700
1300
4700
1300
Min
600
250
100
range is described in
( 4)
0
0
–40°C ≤ T
1000
1000
3450
Max
300
300
300
300
300
900
40
50
50
A
≤ +125°C (Extended)
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC/DC characteristics
© 2009 Microchip Technology Inc.
2
C bus specification) before
1.8V-5.5V
C
C
Time the bus must be free
2.7V-5.5V
1.8V-5.5V
2.7V-5.5V
10 to 400 pF
C
10 to 400 pF
C
10 to 400 pF
10 to 400 pF
1.8V-5.5V, Note 6
2.7V-5.5V, Note 6
( 2)
( 1)
before a new transmission
can start
Philips Spec states N.A.
b
b
b
b
is specified to be from
is specified to be from
is specified to be from
is specified to be from
2
C-bus system, but the
2
C specification, but
Conditions

Related parts for MCP40D17