EM6520 EM Microelectronic, EM6520 Datasheet - Page 9

• Manufacturer Part Number: EM6520
• Description: MFP version of EM6620 Ultra Low Power Microcontroller 4x8 LCD Driver
• Manufacturer: EM Microelectronic

4.1 Oscillation Detection Circuit
At power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry,
and thus the system reset. The CPU of the EM6520 remains in the reset state for the ‘CPU Reset Delay’, to
allow the oscillator to stabilize after power up.
The oscillator is disabled during sleep mode. So when waking up from sleep mode, the CPU of the EM6520
remains in the reset state for the ‘CPU Reset Delay’ , to allow the oscillator to stabilize. During this oscillator
stabilization period, the oscillation detection circuit is inhibited.
In active or standby modes, the oscillator detection circuit monitors the oscillator. If it stops for any reason, a
system reset is generated. After clock restart, the CPU waits for the CPU Reset Delay before executing the first
instructions.
The oscillation detection circuitry can be inhibited with NoOscWD = 1 in register RegVLDCntl. At power up, and
after any Reset, the function is activated.
The ‘CPU Reset Delay’ is 32768 system clocks ( ck[16] ) long.
4.2 Input Port A Reset
By writing the OptInpRSel1 and OptInpRSel2 registers it is possible to choose any combination of port A input
values to execute a system reset. The reset condition must be valid for at least 16 ms (system clock = 32 KHz)
in active and standby mode. The applied port A reset condition will immediately trigger a system reset in Sleep
mode.
Bit NoInputReset in option register OptFSelPB selects the input port A reset function in active and standby
mode. If set to "0" the occurrence of the selected combination for input port A reset will trigger a system reset.
Set to ‘1’ the input port A reset function is inhibited.
This option bit has no action in sleep mode, where the occurrence of the selected input port A reset combination
will always immediately trigger a system reset.
Reset combination selection ( InpReset) in registers OptInpRSel1 and OptInpRSel2.
InpReset = InpResPA[0] • InpResPA[1] • InpResPA[2] • InpResPA[3]
n = 0 to 3
i.e. ; - No reset if InpResPA[n] = V
Copyright  2002, EM Microelectronic-Marin SA
InpRes1PA[n] InpRes2PA[n] InpResPA[n]
0
0
1
1
- Don't care function on a single bit with
- Always Reset if InpResPA[3:0] = 'b1111.
its InpResPA[n] = V
0
1
0
1
DD
.
V
PA[n]
not PA[n]
V
SS
SS
DD
.
Figure 7. Input port A reset structure
BIT
BIT
BIT
Input PortA Reset
Bit[3] selection
BIT
[0]
[1]
[3]
[2]
InpRes1PA[3]
InpRes2PA[3]
9
Input PortA Reset
Bit[0] selection
Input PortA Reset
Bit[1] selection
Input PortA Reset
Bit[2] selection
VSS
PA[3]
PA[3]
VDD
0
1 MUX
2
3 1 0
InpResPA[3]
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EM6520
03/02 REV. D/449
InpResPA
Input
Reset
from
PortA