FDC37C665IR SMSC Corporation, FDC37C665IR Datasheet - Page 95

• Manufacturer Part Number: FDC37C665IR
• Description: 3/5 Volt Advanced High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controller with Infranred Support
• Manufacturer: SMSC Corporation

8.Peripheral asserts nWAIT, indicating to the
9.Chip may modify nWRITE and nPDATA in
EPP 1.9 Read
The timing for a read operation (data) is shown
in timing diagram EPP Read Data cycle.
IOCHRDY is driven active low at the start of
each EPP read and is released when it has been
determined that the read cycle can complete.
The read cycle can complete under the following
circumstances:
1.If the EPP bus is not ready (nWAIT is active
2.If the EPP bus is ready (nWAIT is inactive
Read Sequence of Operation
1.The host selects an EPP register and drives
2.The chip drives IOCHRDY inactive (low).
3.If WAIT is not asserted, the chip must wait
4.The chip tri-states the PData bus and
5.
6.
b)The chip latches the data from the SData
host that any hold time requirements have
been satisfied and acknowledging the
termination of the cycle.
preparation for the next cycle.
low) when nDATASTB goes active then
the read can complete when nWAIT goes
inactive high.
high) then the chip must wait for it to go
active low before changing the state of
WRITE or before nDATASTB goes active.
The read can complete once nWAIT is
determined inactive.
nIOR active.
until WAIT is asserted.
deasserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR
is set and the nWRITE signal is valid.
Peripheral drives PData bus valid.
already done so, the peripheral should
latch the information byte now.
bus for the PData bus and asserts
(releases) IOCHRDY allowing the host
to complete the write cycle.
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7.
8.
9.
10. Chip
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the
SPP Control Port and direction is controlled by
PCD of the Control port.
In EPP mode, the system timing is closely
coupled to the EPP timing. For this reason, a
watchdog timer is required to prevent system
lockup. The timer indicates if more than 10usec
have elapsed from the start of the EPP cycle
(nIOR or nIOW asserted) to the end of the cycle
nIOR or nIOW deasserted).
occurs, the current EPP cycle is aborted and the
time-out condition is indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bits D0, D1
and D3 are set to zero. Also, bit D5 (PCD) is a
logic "0" for an EPP write or a logic "1" for and
EPP read.
Peripheral deasserts nWAIT, indicating that
termination phase of the cycle.
a)
b)
Peripheral tri-states the PData bus and
asserts nWAIT, indicating to the host that
the PData bus is tri-stated.
nPDATA in preparation for the next cycle.
PData is valid and the chip may begin the
The chip latches the data from the
PData
deasserts nDATASTB or nADDRSTRB,
this marks
termination phase.
The chip drives the valid data onto the
SData bus and asserts (releases)
IOCHRDY
complete the read cycle.
may modify nWRITE, PDIR
bus
allowing
for
the beginning of the
the
the
If a time-out
SData
host
and
bus,
to