AN2866 Freescale Semiconductor / Motorola, AN2866 Datasheet - Page 16

• Manufacturer Part Number: AN2866
• Description: Migrating from the MC68332 to the ColdFire MCF523x
• Manufacturer: Freescale Semiconductor / Motorola

Device Differences
peripheral devices, the processing of the IACK cycle directly negates the interrupt request, while other
devices require that request to be explicitly negated during the processing of the service routine.
For the MCF523x, the processing of the interrupt acknowledge cycle is fundamentally different than on
the MC68332. In the new approach, all IACK cycles are directly handled by the interrupt controller, so
IACK cycles are not routed to the requesting peripheral device or the external bus. Instead, every interrupt
source (including external interrupt requests on the IRQ[7:1] pins) has a fixed vector assignment.
The MCF523x has a set of interrupt control registers (ICR1–ICR63) that has the same functionality as the
MC68332’s QSM Interrupt Level Register (QILR). That is, they assign an interrupt priority to each of the
interrupt sources. The difference here is that the ColdFire architecture supports a priority scheme in which
there is both a priority and a level that define an interrupt’s overall priority. There are 9 priorities associated
with each of the 7 levels of interrupts for a total of 63 unique interrupt priority levels. (It is important that
each interrupt source is assigned a unique priority level to guarantee proper operation of the interrupt
controller.) Eight of the nine priorities are assignable to each of the interrupt sources. The ninth priority
within each interrupt level is a fixed priority interrupt and is automatically assigned to the external IRQ
interrupts. The priority and level for these interrupts are fixed such that IRQ1 is the fixed priority interrupt
within level 1, IRQ2 is the fixed priority interrupt within level 2, and so on through IRQ7 for level 7. These
fixed-priority interrupts have a priority at the midpoint of the 9 priorities within each level such that
priority 0 (lowest priority) through priority 3 are lower priority than the fixed priority (IRQn) for a
particular level, while priority 4 through priority 7 (highest priority) have a higher priority than the fixed
priority for a particular level.
Since there are more than 63 interrupt sources on the MCF523x, there are two instantiations of the interrupt
controller used to assign levels and vectors to all of the on-chip and off-chip interrupt sources—INTC0
and INTC1. When both interrupt controllers have active interrupts at the same level and priority, then the
INTC0 interrupt will be serviced first. If INTC1 has an active interrupt that has a higher level or priority
than the highest active INTC0 interrupt, then the INTC1 interrupt will be serviced first.
Once the MCF523x’s ICRs are programmed with the desired priority and level for each interrupt source,
then that interrupt source’s interrupts are enabled by clearing the corresponding bit in the interrupt mask
registers (IMRH and IMRL). There is a bit in these two 32-bit registers for each possible interrupt source
associated with the interrupt controller, plus another bit that masks all interrupts regardless of the
individual mask bit settings. This level of masking is in addition to the interrupt masking using the status
register’s interrupt priority mask field that is used on both the MC68332 and the MCF523x.
These are the basic control differences between the interrupt controllers in these two devices. This section
is not the extent of the interrupt servicing and exception handling considerations that need to be examined.
However, it does highlight the differences in interrupt control methodology between the two devices.
2.4.1.8
External Interrupt Pins vs. Edge Port (EPORT)
The MC68332 has seven active low external interrupt pins (IRQ[7:1]). Similarly, the MCF523x has up to
seven interrupt signals IRQ[7:1] as part of the Edge Port (EPORT) module. The EPORT provides
additional programmability for interrupt triggering. The MC68332 only level detects interrupts, but each
of the MCF523x’s external interrupt pins can be configured for level-sensitive, rising edge triggered,
falling edge triggered, or falling and rising edge triggered interrupts on a pin-by-pin basis.
Table 5
contrasts the features of the MC68332’s interrupts pins and the MCF523x’s EPORT.
®
Migrating from the MC68332 to the ColdFire
MCF523x, Rev. 1.0
16
Freescale Semiconductor