AN2866 Freescale Semiconductor / Motorola, AN2866 Datasheet - Page 15

• Manufacturer Part Number: AN2866
• Description: Migrating from the MC68332 to the ColdFire MCF523x
• Manufacturer: Freescale Semiconductor / Motorola

2.4.1.6
The MC68332 and MCF523x both include a software watchdog timer. As with the PITs, the functionality
of the modules is very similar; however, the MCF523x family offers a wider range of time-out values. The
MCF523x’s watchdog has a 16-bit prescaler register, whereas the MC68332 only has eight prescaler
options.
2.4.1.7
The interrupt architecture of ColdFire is exactly the same as the CPU32 family. A 3-bit encoded interrupt
priority level is sent from the interrupt controller to the core, providing 7 levels of interrupt requests. Level
7 represents the highest priority interrupt level, while level 1 is the lowest priority. The processor samples
for active interrupt requests once per instruction by comparing the encoded priority level against a 3-bit
interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If the priority level is
greater than the SR[I] field at the sample point, the processor suspends normal instruction execution and
initiates interrupt exception processing. Level 7 interrupts are treated as non-maskable and edge-sensitive
within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the
value of the SR[I] field. For correct operation, the ColdFire architecture requires that, once asserted, the
interrupt source remain asserted until explicitly disabled by the interrupt service routine.
During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then
fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt
acknowledge (IACK) cycle, with the ColdFire implementation using a special encoding of the transfer
type and transfer modifier attributes to distinguish this data fetch from a “normal” memory access. The
fetched data provides an index into the exception vector table that contains 256 addresses, each pointing
to the beginning of a specific exception service routine. In particular, vectors 64 - 255 of the exception
vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for
the processor to handle reset, error conditions (access & address), arithmetic faults, system calls, etc. Once
the interrupt vector number has been retrieved, the processor continues by creating a stack frame in
memory. For ColdFire, all exception stack frames contain 32 bits of vector and status register data, and the
32-bit program counter value of the instruction that was interrupted (refer to the MCF5235 Reference
Manual for more information on the stack frame format). After the exception stack frame is stored in
memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number
as the offset, and then jumps to that address to begin execution of the service routine. After the status
register is stored in the exception stack frame, the SR[I] mask field is set to the level of the interrupt being
acknowledged, effectively masking that level and all lower values while in the service routine. For many
Freescale Semiconductor
Watchdog Timer
Interrupt Controller (INTC)
Programmable interrupt request level
Migrating from the MC68332 to the ColdFire
Table 4. MC68332 and MCF523x PIT Feature Differences
Prescaler values
Number of PITs
Modulus values
Feature
MC68332
1 or 512
1–255
®
1
√
MCF523x, Rev. 1.0
2
n
MCF523x
1–65536
(n = 1–16)
4
√
Device Differences
15