AN2667 Freescale Semiconductor / Motorola, AN2667 Datasheet - Page 4

• Manufacturer Part Number: AN2667
• Description: Multi-Controller Hardware Development for the MPC5xx Family
• Manufacturer: Freescale Semiconductor / Motorola

3. System Configuration Issues
The following is a list of questions commonly asked when designing a multi-MPC5xx
system:
The remainder of this document addresses these questions and provides the answers
which ultimately allow customers to successfully design their own system.
3.1
The devices within a multi-MPC5xx system communicate with one another across the
External Bus Interface. As shown below in Figure 3.1 the transfer is initiated with the
assertion of Transfer Start. The internal address of the other controller is also presented
at this point along with R / #W. The slave device latches the address within the same
clock cycle. The slave device fetches the data and presents it on the bus. The master
device then latches the data within the same clock that the slave presents the data. The
cycle is terminated by the TA (successful transfer), TEA(unsuccessful transfer) or
RETRY.
RETRY is provided to solve a deadlock that may occur when the core of device
to perform an external access but the external bus is busy because of an access of
another device
encountered, RETRY is asserted to give device B a signal to release the external bus
and to retry its access later giving device A the opportunity to complete its access.
The Burst Inhibit (BI) signal may be required when an external master cannot perform
burst accesses to internal resources because the slave interface does not support
bursts. Generally speaking the BI line is optional, because the MCU requests bursts
only for instruction fetches. Thus if the multiprocessor system is designed in a way that
one processor does not fetch instructions from internal memories of another one, the BI
line is not required.
If there are only two MPC5xx devices within the system the bus arbitration can be
handled by the arbiter in either device. The arbiter can be selected by setting or clearing
the SIUMCR [EARB].If this bit is set then external arbitration on the external bus is
assumed in which case internal arbitration should be selected on the second device.
This would mean SIUMCR[EARB] should be programmed as “1” and “0” on each
respective device. If there are more than two chips in the system, the only choice is to
use some other external arbiter.On the device where SIUMCR [EARB] = “0”, there is a
MOTOROLA
1. How do the MPC5xx devices communicate with one another?
2. How is each device differentiated?
3. How is Master/Slave/Peripheral mode selected?
4. How is reset controlled on both devices?
5. What is the clocking strategy?
6. How is each device initialised?
7. How is debug handled?
How do the MPC5xx devices communicate with one another?
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B to some internal address of device A. Once this situation is
Multi-Controller Hardware Development for the MPC5xx Family
Freescale Semiconductor, Inc.
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A tries
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