AN2530 Freescale Semiconductor / Motorola, AN2530 Datasheet - Page 5

• Manufacturer Part Number: AN2530
• Description: Standard Space Vector Modulation with Dead-Time Correction TPU Function Set
• Manufacturer: Freescale Semiconductor / Motorola

Detailed Function Description
Standard Space
Vector Modulation
with Dead-Time
Correction – Top
(svmStdDt_top)
and Standard Space
Vector Modulation
with Dead-Time
Correction – Bottom
(svmStdDt_bottom)
MOTOROLA
Standard Space Vector Modulation with Dead-Time Correction TPU Function Set (svmStdDt)
NOTE:
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
The svmStdDt_top and svmStdDt_bottom TPU functions work together to
generate a 6-channel, 3-phase PWM signal, with dead-time between the top
and bottom channels. In order to charge the bootstrap transistors, the PWM
signals start to run 1.6ms after their initialization (at 20MHz TCR1 clock). The
functions generate signals corresponding to Reference Voltage Vector
Amplitude of 0 (50% duty-cycle) until the first reloaded values are processed.
The CPU controls the PWM output by setting the TPU parameters. The Stator
Reference Voltage Vector components u
time. The PWM period T and the prescaler – the number of PWM periods per
reload of new values – are also read at each reload, so these parameters can
be changed during run time. Conversely, dead-time (DT) and minimum pulse
width (MPW) are not supposed to be changed during run time. The phase
currents currentA, currentB and currentC are read by the TPU asynchronously
to the PWM parameters reload. They are read in the last part of edge-time
calculation to reflect the latest state of the phase currents. The CPU notifies the
TPU that the new reload values are prepared by setting the LD_OK parameter.
The TPU notifies the CPU that the reload values have been read and new
values can be written by clearing the LD_OK parameter.
4. Issues an HSR (Host Service Request) type %10 to one of the
5. Enables servicing by assigning high, middle or low priority to the channel
Freescale Semiconductor, Inc.
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svmStdDt_sync channel or an svmStdDt_res channel is used, then also
its parameters must be set before initialization.
svmStdDt_bottom channels to initialize all PWM channels. Issues an
HSR type %10 to the svmStdDt_sync channels, svmStdDt_res channels
and svmStdDt_fault channel, if used.
priority bits. All PWM channels must be assigned the same priority to
ensure correct operation. The CPU must ensure that the
svmStdDt_sync or svmStdDt_res channels are initialized after the
initialization of PWM channels:
–
–
–
assign a priority to the PWM channels to enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the PWM channels has completed and
assign a priority to the svmStdDt_sync or svmStdDt_res channels to
enable their initialization
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á
and u
â
have to be adjusted during run
Detailed Function Description
AN2530/D
5