AN2530 Freescale Semiconductor / Motorola, AN2530 Datasheet - Page 16

• Manufacturer Part Number: AN2530
• Description: Standard Space Vector Modulation with Dead-Time Correction TPU Function Set
• Manufacturer: Freescale Semiconductor / Motorola

AN2530/D
16
top channel
top channel
bottom channel
bottom channel
time slot sequence
time slot sequence
Standard Space Vector Modulation with Dead-Time Correction TPU Function Set (svmStdDt)
TST
TST
10 IMB clock cycles. The service starts immediately after the top channel high
to low transition, which occurs at a period of DT before the bottom channel low
to high transition (see
IMB clock cycles – DT. The svmStdDt functions are designed so that no other
svmStdDt state can request service at this time. The MPW, in the case when
only svmStdDt functions are running on one TPU, is then
and is a minimum at least 16 IMB clock cycles (when latency = 0).
Note that the MPW, as well as the DT, are not entered into the parameter RAM
in IMB clock cycles, but in TCR1 clock cycles. It is recommended for the
svmStdDt function to configure the TCR1 clock to its maximum speed, which is
the IMB clock divided by 2. In this case the MPW = 31 – DT, with a minimum
value of 8.
When other functions are running together, on the same TPU, with the
svmStdDt functions, the latency could be lengthened. To maintain sufficiently
high performance of svmStdDt, it is recommended that the following rules are
followed when configuring the TPU:
In this instance, one of the two worst case timing cases can happen. These are
illustrated in
= 36 IMB clock cycles + 10 IMB clock cycles – DT + 16 IMB clock cycles =
•
•
Freescale Semiconductor, Inc.
Figure 8. Worst case timing – case one
For More Information On This Product,
H
H
assign svmStdDt PWM channels high priority
assign svmStdDt PWM functions on low channel numbers so that no
other function with high priority is assigned a channel with a lower
number
DT
DT
Figure 8
TST
TST
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M
M
Figure
and
TST+4
TST+4
latency + 16 IMB clock cycles =
= 62 IMB clock cycles – DT
Figure
7), so that the latency is 36 IMB clock cycles + 10
LH_C5
LH_C5
latency
latency
H
H
9. Which case occurs depends on the DT.
MPW
MPW
TST
TST
L
L
TST+4
TST+4
HL
HL
H
H
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