AN2531/D Motorola / Freescale Semiconductor, AN2531/D Datasheet - Page 5

• Manufacturer Part Number: AN2531/D
• Description: Standard Space Vector Modulation with Dead-Time Correction - XOR version TPU Function Set
• Manufacturer: Motorola / Freescale Semiconductor

Detailed Function Description
Standard Space
Vector Modulation
with Dead-Time
Correction – XOR
version – R channels
(svmStdDtXor_R)
and Standard Space
Vector Modulation
with Dead-Time
Correction – XOR
version – T channels
(svmStdDtXor_T)
MOTOROLA
NOTE:
Standard SVM with Dead-Time Correction – XOR version (svmStdDtXor)
A CPU routine that configures the TPU can be generated automatically using
the MPC500_Quick_Start Graphical Configuration Tool.
The svmStdDtXor_R and svmStdDtXor_T TPU functions work together to
generate 6 pairs of XOR gate inputs. The XOR gate outputs then produce a 6-
channel 3-phase center-aligned PWM signal with dead-time between the top
and bottom channels. In order to charge the bootstrap transistors, the PWM
signals start to run 1.6ms after their initialization (at 20MHz TCR1 clock). The
functions generate signals corresponding to Reference Voltage Vector
Amplitude of 0 (50% duty-cycle) until the first reloaded values are processed.
The CPU controls the PWM output by setting the TPU parameters. The Stator
Reference Voltage Vector components u
run time. The PWM period T and the prescaler – the number of PWM periods
per reload of new values – are also read at each reload, so these parameters
can be changed during run time. Conversely, dead-time (DT) is not supposed
to be changed during run time. The phase currents currentA, currentB and
currentC are read by the TPU asynchronously to PWM parameters reload.
They are read in the last part of the edge-time calculation to reflect the latest
state of the phase currents. The CPU notifies the TPU that the new reload
values are prepared by setting the LD_OK parameter. The TPU notifies the
CPU that the reload values have been read and new values can be written by
clearing the LD_OK parameter.
5. Enables servicing by assigning a high, middle or low priority to the
Freescale Semiconductor, Inc.
For More Information On This Product,
svmStdDtXor_sync channels, svmStdDtXor_res channels and
svmStdDtXor_fault channel, if used.
channel priority bits. All svmStdDtXor_R and svmStdDtXor_T channels
must be assigned the same priority to ensure correct operation. The
CPU must ensure that the svmStdDtXor_sync or svmStdDtXor_res
channels are initialized after the initialization of the StdDtXor_R and
svmStdDtXor_T channels:
–
–
–
assign a priority to the StdDtXor_R and svmStdDtXor_T channels to
enable their initialization
if a Synchronization Signal or a Resolver Reference Signal channel
is used, wait until the HSR bits are cleared to indicate that
initialization of the StdDtXor_R and svmStdDtXor_T channels has
completed and
assign a priority to the svmStdDtXor_sync or svmStdDtXor_res
channels to enable their initialization
Go to: www.freescale.com
á
and u
â
have to be adjusted during
Detailed Function Description
AN2531/D
5