AN2414 Freescale Semiconductor / Motorola, AN2414 Datasheet - Page 4

• Manufacturer Part Number: AN2414
• Description: CMOS Signal Interface (CSI) Module Supplementary Information for MC9328MX1 and MC9328MXL Application Note
• Manufacturer: Freescale Semiconductor / Motorola

Sensor Interface Operation
HSYNC is an active high signal that encapsulates valid pixel clocks. HSYNC & PIXCLK are passed
through a logical-AND operation to generate valid pixel clocks.
HSYNC & PIXCLK => Valid PIXCLK
So, data is latched on every valid pixel clock.
3.2 Non-Gated Clock Mode
Frame starts with a pulse on VSYNC. This triggers a SOF interrupt and resets the internal logic at the same
time. The polarity of SOF is programmable, i.e. triggered by rising or falling edge.
HSYNC is ignored in this case. Every incoming pixel clock is treated as valid and leading to a data-latch
operation.
Motorola sensors fall into this category.
Typical pin connection for Motorola sensor is:
In this case, BLANK signal on sensor is exactly matching with what we expect to have on HSYNC.
However, since there is no dummy pixel clock, i.e all pixel clocks going from sensor are valid, there is no
need to enable Gated-clock mode, although it is not harmful to have this mode enabled.
3.3 CCIR656 Mode
There is no direct support on CCIR656 interface. The CSI is only able to receive raw data stream but not to
do any decoding. Decoding should rely on software, in expense of computing loading.
4
Start Of Frame
Horizontal Sync
Bayer Data
Pin Name
Freescale Semiconductor, Inc.
For More Information On This Product,
MC9328MX1/MXL Application Note
SOF
BLANK
ADC[9..2]
ADC[1..0]
Engineering Draft / Preliminary
Go to: www.freescale.com
Sensor
Figure 5.
Table 1.
VSYNC
HSYNC (Ignored)
D[7..0]
Ignored
MX1
MOTOROLA