CY2SSTV16857 SpectraLinear, CY2SSTV16857 Datasheet

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... LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Pin Configuration Tel:(408) 855-0555 Fax:(408) 855-0550 CY2SSTV16857 VSS 3 ...

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... Data outputs, SSTL_2, Class II output. D(1:14) I Data input clocked on the crossing of the rising edge of CLK, and the falling edge of CLK. CLK, CLK I/I Differential clock input. VDDQ Power Power supply voltage quiet, 2.5V nominal. VREF I Input reference voltage, 1.25V nominal. CY2SSTV16857 Description Page ...

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... JEDEC (JESD 51) By design and verification By design and verification = Temperature = 0°C to +85 °C) DD Description PC1600,2100,2700 PC3200 PC3200 PC1600,2100,2700 /2) PC3200 RESET RESET DDQ 100 DDQ V = 2.3V DD CY2SSTV16857 < < out Condition Min. Max. 2.3 2 ±50 > V ± – ...

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... Fast slew rate, (see notes 5 and 7), Data before CLK, CLK Slow slew rate, (see notes 6 and 7), Data before CLK, CLK Fast slew rate, (see notes 5 and 7), Data after CLK, CLK Slow slew rate (see notes 6 and 7), Data after CLK, CLK CY2SSTV16857 Condition Min. Typ. = 2.3V to 2.7V – ...

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... CY2SSTV16857 V = 2.5V ± 0.2V DD Min. Max. Unit 280 1.1 2.8 ns 4.3 ns 0.85 4 V/ns 1.0 4 V/ns Pull-Up Min I (mA) Max I (mA –5 –15 –10 –27 –15 –38 –19 –49 –23 –60 – ...

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... DDQ Min. Max. 4 V/ns Figure 3. Voltage Waveforms Propagation Delay Times 4 V/ns VI(PP) VICR Figure 4. Voltage Waveforms Propagation Delay Times VIH** VREF* VREF* VIL*** [11, 13, 14] CY2SSTV16857 LVCMOS RESET VDD/2 VDD/2 Input t t inact act IDD 90% 10% Low- and High-level Enabling VICR VICR Input t ...

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... CY2SSTV16857ZI 48-pin TSSOP CY2SSTV16857ZIT 48-pin TSSOP –Tape and Reel Lead-Free CY2SSTV16857ZXC 48-pin TSSOP CY2SSTV16857ZXCT 48-pin TSSOP –Tape and Reel www.DataSheet4U.com CY2SSTV16857ZXI 48-pin TSSOP CY2SSTV16857ZXIT 48-pin TSSOP –Tape and Reel Package Drawing and Dimensiona 0.500[0.019 0.500[0.020] 0.851[0.033] BSC ...