AN2320 Freescale Semiconductor / Motorola, AN2320 Datasheet - Page 7

• Manufacturer Part Number: AN2320
• Description: Interfacing the MCF5272 to a Standalone CAN Controller
• Manufacturer: Freescale Semiconductor / Motorola

Infineon has added an optional fifth signal, a ready signal (RDY), to the standard SPI interface. This is a
handshake signal, which can be used to indicate when the serial interface can be accessed by the host.
However this RDY signal is not required provided the SSC timings detailed in Section 2.1.3, “Timing” are
adhered to. While it would be a simple case of connecting the ready input signal to a GPIO pin on the
MCF5272 and reading the level before accessing the CAN controller, the MCF5272 QSPI programmable
delays before and after transfer means the timing specifications can be met without using the RDY signal.
2.1.3
Figure 4 gives the 82C900 SSC timing requirements that must be met in the absence of a ready signal that
indicates to the host when a transfer is allowed. A consecutive-read access and a consecutive-write access
are shown. The first byte transferred is the address and any subsequent transfers are data bytes which are
read or written to consecutive addresses starting at the address defined. In this mode, the chip-select signal
must remain active until the transfer of all data for that access is complete.
All timing requirements, except minimum delay after reset (see Section 2.3, “Reset”), are met by
programming the QSPI clock delay and the QSPI delay after transfer on the MCF5272. The QSPI clock
delay determines the delay between chip-select assertion and the first valid serial clock transition, and the
QSPI delay after transfer determines the delay after each serial transfer. In Figure 4, the clock delay is
programmed to meet specification (A), while the delay after transfer is programmed to meet all other timing
requirements. The delay after transfer is inserted not only on the negation of the chip-select signal (E) but
also between data transfers (B, C, F and G) and following the final data transfer (D) of consecutive reads or
writes.
The QSPI clock delay (SCLK
equations:
QCD has a range of 1-127, DTL has a range of 1-255 and CLKIN is the system clock frequency.
For a 66MHz system clock, the QSPI clock delay is programmable between 15ns and 1.9 s, and the delay
after transfer is programmable between 485ns and 124 s (with the option of using a standard delay of
258ns). A QCD of 6 (90ns delay) and a DTL of 2 (970ns) were chosen to meet the worst case specifications
shown in Figure 4.
MOTOROLA
SCLK
TxRx
DELAY
DELAY
=
Timing
=
32 DTL
----------------------- -
------------------ -
CLKIN
CLKIN
QCD
Interfacing the MCF5272 to a Standalone CAN Controller
Freescale Semiconductor, Inc.
DELAY
For More Information On This Product,
) and the delay after transfer (TxRx
Go to: www.freescale.com
DELAY
) are defined by the following
SPI Interface
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