AN2320 Freescale Semiconductor / Motorola, AN2320 Datasheet - Page 16

• Manufacturer Part Number: AN2320
• Description: Interfacing the MCF5272 to a Standalone CAN Controller
• Manufacturer: Freescale Semiconductor / Motorola

82C900 Initialisation
}
/*The upper 4 bits of the register address are passed.*/
void CAN_SetPageReg(uint8 PageNumber)
{
/*Page register address. Can be accessed regardless of its contents*/
/*Write upper four bits to PAGE register and enable auto increment*/
}
To optimise data transfer between the host and the 82C900, the SSC can transfer a data stream upon the
transmission of a single address. This is illustrated in Figure 4. The control bit for incrementing the address
during these consecutive-read and consecutive-write accesses is contained in the PAGE register. When set,
the contents of the address register are automatically incremented by one after each data-byte transfer.
Incrementing is stopped at the boundaries between CAN message objects to prevent unintended corruption
of CAN messages. Accidentally overwriting the PAGE register is also prevented.
3.3
The 82C900 initialisation software logically connects CAN nodes A and B to a CAN bus and allows them
to participate in message transfer. Initialisation is required after the controller is reset by the MCF5272
processor and after the occurrence of a ‘bus off’ event, both of which will logically disconnect a node from
its associated bus.
The code used to configure the CAN nodes is given below. During initialisation the CAN node must be
disconnected from the bus; any interrupts must be reset and the baud rate must be defined. This involves
updating the node control registers (ACR/BCR) and bit timing registers (ABTR, BBTR) for both CAN
nodes and configuring the interrupt mask register for CAN node B to generate an interrupt when a message
is received.
The node control registers control the initialisation process, control node-specific interrupts, and define the
operating mode. The bit field descriptions of the lower 16 bits of the register are given in Figure 7 below.
16
MCF5272_WR_QSPI_QDR(imm,Data);
MCF5272_WR_QSPI_QWR(imm,MCF5272_QSPI_QWR_SendByte);
MCF5272_WR_QSPI_QDLYR(imm,MCF5272_QSPI_QDLYR_CanEnable);
while (!(MCF5272_RD_QSPI_QIR(imm) & MCF5272_QSPI_QIR_QSPIFinish))
MCF5272_IMM *imm = mcf5272_get_immp();
MCF5272_WR_QSPI_QAR(imm,MCF5272_QSPI_QAR_Tx);
MCF5272_WR_QSPI_QDR(imm,CAN_PAGE|CanWriteMask);
MCF5272_WR_QSPI_QDR(imm,PageNumber|CanAutoInc);
MCF5272_WR_QSPI_QWR(imm,MCF5272_QSPI_QWR_SetPageReg);
MCF5272_WR_QSPI_QDLYR(imm,MCF5272_QSPI_QDLYR_CanEnable);
while (!(MCF5272_RD_QSPI_QIR(imm) & MCF5272_QSPI_QIR_QSPIFinish))
82C900 Initialisation
;
;
Interfacing the MCF5272 to a Standalone CAN Controller
Freescale Semiconductor, Inc.
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