CY2PP3115 Cypress Semiconductor, CY2PP3115 Datasheet - Page 2

• Manufacturer Part Number: CY2PP3115
• Description: Differential Fanout Buffer
• Manufacturer: Cypress Semiconductor

Document #: 38-07502 Rev.*A
Pin Description
Table 1. Function Table
Governing Agencies
The following agencies provide specifications that apply to the
CY2PP3115. The agency name and relevant specification is
listed below.
1,14,27, 30, 39, 40, 47,
52
2
3,4,11,12
5,8
6,9
10
13
28,29
7
26,24,22,20,18,16
25,23,21,19,17,15
38,36,34,32
37,35,33,31
46,44,42
45,43,41
51,49
50,48
FSELA (Asynchronous)
FSELB (Asynchronous)
FSELC (Asynchronous)
FSELD (Asynchronous)
CLK_SEL (Asynchronous)
MR (Asynchronous)
JEDEC
IEEE
UL
Mil–Spec
Notes:
1.
2.
3.
In the I/O column, the following notation is used: I for Input, O for Output, PD for Pull-down, PU for Pull-up, PC for Pull Center, O for output, OE for open emitter
and PWR for Power.
In ECL mode (negative power supply mode), V
V
and are between VCC and VEE.
V
EE
BB
Agency Name
is connected to GND (0V) and V
is available for use for single ended bias mode when V
Pin No.
Control Pin
VCC
MR
FSEL(A,B,C,D)
CLK(0:1)
CLK(0:1)#
VBB
VEE
NC
CLK_SEL
QD(0:5)
QD(0:5)#
QC(0:3)
QC(0:3)#
QB(0:2)
QB(0:2)#
QA(0:1)
QA(0:1)#
Name
JESD 51 (Theta JA)
JESD 8–2 (ECL)
JESD 65–A (skew,jitter)
1596.3 (Jitter specs)
94 (Flammability Grading)
883E Method 1012.1
(Thermal Theta JC)
CC
[2,3]
is either +3.3V or +2.5V. In both modes, the input and output levels are referenced to the most positive supply (V
Specification
EE
+PWR
I,PD
I,PD
I,PD
I,PC
O
–PWR
I,PD
O,OE
O,OE
O,OE
O,OE
O,OE
O,OE
O,OE
O,OE
is either –3.3V or –2.5V and V
I/O
[1]
PRELIMINARY
CC
POWER
ECL/PECL
ECL/PECL
ECL/PECL
Bias
POWER
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
ECL/PECL
is +3.3V.
Type
Active
CLK0
÷1
÷1
÷1
÷1
0
Power Supply, positive connection
Reset
Output Divider Selects
Differential Clock Inputs – TRUE
Differential Clock Inputs – COMPLIMENT
DC Bias Source
Power Supply, Negative Connection
No Connect. Pad Only
Clock Input Select
Bank D True Output
Bank D Compliment Output
Bank C True Output
Bank C Compliment Output
Bank B True Output
Bank B Compliment Output
Bank A True Output
Bank A Compliment Output
CC
is connected to GND (0V). In PECL mode (positive power supply mode),
Description
Reset (QX = L and QX# = H)
FastEdge™ Series
CLK1
÷2
÷2
÷2
÷2
1
CY2PP3115
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