AN2316 Freescale Semiconductor / Motorola, AN2316 Datasheet - Page 6

• Manufacturer Part Number: AN2316
• Description: Connecting an MSC8102 TDM to a Time-Slot Interchange Switching Device
• Manufacturer: Freescale Semiconductor / Motorola

Configuring the PEF24471 (TSI)
1.5 External Interface
1.6 TDM Activation
2
6
Configuring the PEF24471 (TSI)
The TDM interface is essentially a set of I/O pins that can configured for either a peripheral or a
general-purpose function. The multiplexed peripheral pins for the TDM configured through the parallel
I/O registers (PSOR, PDIR, and PAR).
TDM0 is enabled as follows:
• Reset the event registers (TDM0RER and TDM0TER) by writing a value of 0x32xF to these registers
• Activate the receiver and transmitter by setting the TDM0RCR and TDM0TCR register to 32x1.
An E1 interface is implemented between the MSC8102 TDM and the Infineon-PEF24471 TSI modules.
The TSI is configured to supply a clock frequency of 2.048 MHz and a frame sync frequency of 8 KHz.
The IN0 port is connected internally to OUT and port IN1 is connected internally to OUT1.The write and
read to/from the TSI occurs via the memory controller port. The read and the write access is a standard
8-bit microprocessor interface. Table 7 shows the steps in configuring the TSI.
TDM0TDBST[TDBST] = 0x000038
TDM0RDBFT[RDBFT] = 0x000018
TDM0RDBST[RDBST] = 0x000038
Register Setting Summary:
Set the external frequency to 16 MHz.
Wait 800 ns.
PSOR = 0x07B00000
PODR = 0x00000000
PDIR = 0x00000000
PAR = 0x07F00000
Register Setting
Bits fields Setting
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 5. Receive and Transmit Threshold Registers (Continued)
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Description
Table 6. Parallel I/O Registers
TDM0TSYN,TDM0TDAT,TDM0TDAT,TDM0RDAT, and TDM0RSYN ports
are dedicated peripheral functions.
All the I/O ports are actively driven as outputs.
All the I/O ports counteract as inputs (the TDM determines the direction of
the port).
TDM0TSYN,TDM0TDAT,TDM0TDAT,TDM0RDAT,TDM0RSYN, and
TDM0TCLK ports are dedicated peripheral ports.
Table 7. TSI Configuration
The transmit second threshold interrupt is generated when the second
half of the data buffer is empty.
The receive first threshold interrupt is generated when the first half of the
data buffer is full.
The receive second threshold interrupt is generated when the second
half of the data buffer is full
TDM0RDBFT = 0x00000018, TDM0RDBST = 0x00000038,
TDM0TDBFT = 0x00000018, TDM0TDBST = 0x00000038
Description
Description
Write a value of 0x51 to CMDR2.
Read ISTA1, which should contain a
value of 0x81.
Register Setting