AN2313 Freescale Semiconductor / Motorola, AN2313 Datasheet - Page 8

• Manufacturer Part Number: AN2313
• Description: Connecting an MSC8102 TDM to an MSC8101 Device
• Manufacturer: Freescale Semiconductor / Motorola

Configuring the MSC8101 MCCs
3.3 MCC Control Registers
3.4 Channel-Specific Parameters
8
Part of the global set-up is to initialize the three main MCC control registers:
• MCCF1. Defines the mapping of an MCC channel block to a TDM pin interface. In example discussed
• MCCM1. The interrupt mask register filter interrupt event request to the SC140 core. We set MCCM1
• MCCE1. The interrupt Event Register report receive and transmit event. This register is cleared by
The main channel-specific parameters include maximum receive frame size, allowable SC140 core
interrupts, start-up parameters for channels, and selection of transparent or HDLC protocol for an
individual channel. The channel-specific parameters are located in DPRAM at offset 64 (channel
number). For example, channel 2 is located at address 0x14700080. Table 11 describes the
channel-specific parameters for channel 0, but these parameters are identical for all channels.
here, the four channels route to the TDMA port, so the MCCF1 register value is 0x0.
to a value of 0xFFFF to enable all the interrupts.
writing all ones (MCCE1 = 0xFFFF) at initialization.
0x1470871C
0x1470872C
0x1470873C
0x1470875C
0x14708714
0x14708718
0x14708720
0x14708724
0x1470872E
0x14708730
0x14708734
0x14708738
0x14708740
0x14708744
0x14708748
0x14708750
0x14708754
0x14708758
0x14708760
0x1470874c
Address
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RINTBASE0
RINTBASE1
RINTBASE2
RINTBASE3
SCTPBASE
XTRABASE
C_MASK16
TINTBASE
RINTTMP0
RINTTMP1
RINTTMP2
RINTTMP3
RINTPTR0
RINTPTR1
RINTPTR2
RINTPTR3
TINTPTR
TINTTMP
TS_TMP
DATA1
Name
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Table 10. Global Parameter of MCC1
Width
Hword
Hword
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Field Value
0x2000900
0x2000900
0x2000500
0xB000
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
The transmit interrupt queue base address is
Transmit interrupt queue base address.
The receive interrupt queue base address is
Receive interrupt queue base address.
located in L1 memory at address 0x900
(0x2000900 is the local bus address space).
The extra base parameter information resides in
the DPRAM at address 0xB000.
located in L1 memory at address 0x500
(0x2000500 is the local bus address space).
Field Description