AN2313 Freescale Semiconductor / Motorola, AN2313 Datasheet - Page 10

• Manufacturer Part Number: AN2313
• Description: Connecting an MSC8102 TDM to an MSC8101 Device
• Manufacturer: Freescale Semiconductor / Motorola

Configuring the MSC8101 MCCs
3.6 Circular Interrupt Queues
3.7 Serial Interface RAM
3.8 Clocks and Baud-Rate Generation
10
Each unmasked channel interrupt generated during the transmission and reception of data creates an entry
in an interrupt queue.The receive and transmit entries are held in separate tables. In this example, RINT0
and TINT are used for the receive and transmit interrupts, respectively, as set up in the global parameters.
The interrupt queues are located in L1 memory at addresses 0x500 and 0x900. All entries in the interrupt
tables must be user-initialized with a value of 0x0, except for the last word, which must be initialized
with a value of 0x40000000 (W=1, thus defining the end of the table).
The SIRAM is a block of memory internal to the CPM that routes data from the TDM pins to the MCC.
The SIRAM consists of a series of entries, one set for Tx and one for the Rx flow. Table 13 and Table 14
show the receive and transmit SIRAM configuration.
The TDMA clocks (L1RCLKA and L1TCLKA) are always driven from an external source. In our
example, the receive and transmit clocks are common and they are configured to be driven from the
pin. The CMXSI1 clock route register is set to a value of 0x88.The reference clock is from
BRG0
programed in the BRG configuration register (BRGC1). To give a a clock rate of ~0.5MHz,
set to a value of 0x00010048.
Note:
0x14712000
0x14712002
0x14712004
0x14712006
0x14712400
0x14712402
0x14712404
0x14712406
Address
Address
output is a fraction of the CPM BRGCLK clock and is determined by the division factor
The BRG10 pin must be externally connected to the
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Value
Entry
Value
Entry
0x
0x
0x
0x
0x
0x
0x
0x
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MCC
0x1
0x1
0x1
0x1
MCC
0x1
0x1
0x1
0x1
Table 14. Transmit SI1 RAM
Table 13. Receive SI1 RAM
LOOP
0x0
0x0
0x0
0x0
LOOP
0x0
0x0
0x0
0x0
MCSEL
0x0
0x1
0x2
0x3
MCSEL
0x0
0x1
0x2
0x3
CNT
0x0
0x0
0x0
0x0
CLK9
CNT
0x0
0x0
0x0
0x0
pin.
BYTE
0x1
0x1
0x1
0x1
BYTE
0x1
0x1
0x1
0x1
LST
0x0
0x0
0x0
0x1
LST
0x0
0x0
0x0
0x1
Channel 0 Rx entry
Channel 1 Rx entry
Channel 2 Rx entry
Channel 3 Rx entry
Channel 0 Tx entry
Channel 1 Tx entry
Channel 2 Tx entry
Channel 3 Tx entry
Description
Description
BRG0
BRGC10
. The
CLK9
is