CY2DP1502 Cypress Semiconductor, CY2DP1502 Datasheet

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CY2DP1502

Manufacturer Part Number
CY2DP1502
Description
1:2 LVPECL Fanout Buffer
Manufacturer
Cypress Semiconductor
Datasheet
www.DataSheet4U.net
Features
Cypress Semiconductor Corporation
Document Number: 001-56308 Rev. *G
Logic Block Diagram
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
One low-voltage positive emitter-coupled logic (LVPECL) input
pair distributed to two LVPECL output pairs
20-ps maximum output-to-output skew
480-ps maximum propagation delay
0.15-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 1.5-GHz operation
8-pin small outline integrated circuit (SOIC) or 8-pin thin shrunk
small outline package (TSSOP) package
2.5-V or 3.3-V operating voltage
Commercial and industrial operating temperature range
[1]
V
V
IN
IN#
DD
SS
198 Champion Court
Functional Description
The
low-propagation delay 1:2 LVPECL fanout buffer targeted to
meet the requirements of high-speed clock distribution
applications. The device has a fully differential internal
architecture that is optimized to achieve low additive jitter and
low skew at operating frequencies of up to 1.5 GHz.
CY2DP1502
V
DD
San Jose
1:2 LVPECL Fanout Buffer
,
Q0
Q0#
Q1
Q1#
is
CA 95134-1709
an
ultra-low
Revised April 19, 2011
CY2DP1502
noise,
408-943-2600
low-skew,

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CY2DP1502 Summary of contents

Page 1

... The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies 1.5 GHz. [ IN# • 198 Champion Court CY2DP1502 1:2 LVPECL Fanout Buffer CY2DP1502 is an ultra-low Q0# Q1 Q1# , • San Jose CA 95134-1709 • ...

Page 2

... Operating Conditions....................................................... 3 DC Electrical Specifications ............................................ 4 AC Electrical Specifications ............................................ 5 Ordering Information........................................................ 8 Ordering Code Definition............................................. 8 Document Number: 001-56308 Rev. *G Package Dimensions........................................................ 9 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 CY2DP1502 Page ...

Page 3

... Power supply Condition Nonfunctional Nonfunctional SS Nonfunctional SS Nonfunctional JEDEC STD 22-A114-B At 1/8 in Condition 2.5-V supply 3.3-V supply Commercial Industrial Power-up time for V minimum specified voltage (power ramp must be monotonic). CY2DP1502 Description Min Max –0.5 4.6 –0.5 lesser of 4 0.4 DD –0.5 lesser of 4 0.4 DD –55 150 2000 – ...

Page 4

... See Figure 2 on page 6 [4] Input = V DD [4] Input = V SS Terminated with 50  [5] – 2.0 DD Terminated with 50  [5] – 2.0 DD Measured at 10 MHz; per pin minimum of greater than 200 mV. ID CY2DP1502 Min Max Unit ) – – 0 –0.3 – V 0.4 1.0 V 0.5 V – ...

Page 5

... MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), V > 400 mV ID 50% duty cycle at input, 20% to 80% of full swing ( Input rise/fall time < 1.5 ns (20% to 80%) CY2DP1502 Min Typ Max Unit DC – 1.5 GHz DC – 1.5 GHz 600 – – ...

Page 6

... Figure 4. Input to Any Output Pair Propagation Delay Document Number: 001-56308 Rev Figure 3. Output Differential Voltage Figure 5. Output Duty Cycle PERIOD ODC t PERIOD CY2DP1502 )/2 ICM Page ...

Page 7

... X Document Number: 001-56308 Rev SK1 t SK1 D Figure 7. RMS Phase Jitter Phase noise Offset Frequency f2 f1 RMS Jitter  Area Under the Masked Phase Noise Plot Figure 8. Output Rise/Fall Time 80% 80% 20 CY2DP1502 Phase noise mark V PP Page ...

Page 8

... SOIC tape and reel CY2DP1502SXI 8-Pin SOIC CY2DP1502SXIT 8-Pin SOIC tape and reel CY2DP1502ZXC 8-Pin TSSOP CY2DP1502ZXCT 8-Pin TSSOP tape and reel CY2DP1502ZXI 8-Pin TSSOP CY2DP1502ZXIT 8-Pin TSSOP tape and reel Ordering Code Definition CY 2DP15 02 C/I T SX/ZX Document Number: 001-56308 Rev. *G ...

Page 9

... Package Dimensions Document Number: 001-56308 Rev. *G Figure 9. 8-Pin (150-Mil) SOIC S8 CY2DP1502 51-85066 *D Page ...

Page 10

... Figure 10. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 Document Number: 001-56308 Rev. *G CY2DP1502 51-85093 *C Page ...

Page 11

... Unit of Measure °C degree Celsius dBc decibels relative to the carrier GHz giga hertz Hz hertz k kilo ohm µA microamperes µF micro Farad µs microsecond mA milliamperes ms millisecond mV millivolt MHz megahertz ns nanosecond  ohm pF pico Farad ps pico second V volts W watts CY2DP1502 Page ...

Page 12

... Document History Page Document Title: CY2DP1502 1:2 LVPECL Fanout Buffer Document Number: 001-56308 Orig. of Revision ECN Change ** 2782891 CXQ *A 2838916 CXQ *B 3011766 CXQ *C 3017258 CXQ *D 3100234 CXQ *E 3137726 CXQ *F 3137726 CXQ *G 3234654 VED Document Number: 001-56308 Rev. *G Submission Date 10/09/09 New Datasheet. 01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”. ...

Page 13

... Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-56308 Rev. *G All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB Revised April 19, 2011 CY2DP1502 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 ...

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