CY29972 Cypress Semiconductor, CY29972 Datasheet
CY29972
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CY29972 Summary of contents
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... Frz 2 0 Sync D Q /4, /6, /8, / Frz Sync Pulse Sync Data Generator Frz Output Disable 12 Circuitry < 480 MHz. VCO • 198 Champion Court • CY29972 Buffer [ ...
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... Absolute Maximum Ratings............................................. 7 DC Parameters ..................................................................8 AC Parameters ..................................................................8 Ordering Information ........................................................ 9 Document #: 38-07290 Rev. *D Ordering Code Definition ............................................. 9 Package Drawing and Dimension ................................. 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 CY29972 Page [+] Feedback ...
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... Frequency select inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table Frequency select inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table Frequency select inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2. CY29972 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN ...
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... Serial data input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. – – 3.3 V power supply for output clock buffers. – – 3.3 V power supply for PLL. – – Common ground. CY29972 Description 1. Table 1 on page 1. Page [+] Feedback ...
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... The CY29972 is also capable of providing inverted output clocks. When INV_CLK is asserted HIGH, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the CY29972 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew. ...
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... SYNC Output In situations where output frequency relationships are not integer multiples of each other, the SYNC output provides a signal for system synchronization. The CY29972 monitors the relationship between the QA and QC output clocks. It provides a LOW-going pulse, one period in duration, one period prior to the coincident ...
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... Power Management The individual output enable/freeze control of the CY29972 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks ...
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... V to 2.0 V 0.15 Q (³2) – Q (³4) – Q (³6) – Q (³8) – TCYCLE/2 – 750 2 2 – [10,11] – T QFB = (³8) –270 CLK0 T –330 CLK1 ) transmission lines. DD/2 CY29972 Min Typ Max Unit V – 0 2.0 – – – –120 µA – – 10 µA – – ...
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... Temperature Range Commercial Industrial Package Type AX = 52-pin TQFP Base Device Part Number Company ID Cypress CY29972 Production Flow Industrial, –40 °C to +85 °C Industrial, –40 °C to +85 °C Industrial, –40 °C to +85 °C Industrial, –40 °C to +85 °C Page ...
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... Package Drawing and Dimension 52-Lead Thin Plastic Quad Flat Pack ( 1.0 mm) A52B Document #: 38-07290 Rev. *D CY29972 51-85131 *A Page [+] Feedback ...
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... TQFP Thin quad flat pack Document Conventions Units of Measure Symbol Units of Measure °C degree celsius µA micro amperes mA milli amperes ms milli seconds MHz mega hertz ns nano seconds pF pico farad ps pico seconds V volts Document #: 38-07290 Rev. *D CY29972 Page [+] Feedback ...
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... Document History Page Document Title: CY29972 3.3V, 125-MHz Multi-Output Zero Delay Buffer Document Number: 38-07290 REV. ECN NO. Issue Date ** 111101 02/07/02 *A 122882 12/22/02 *B 387764 See ECN *C 404340 See ECN *D 3270575 06/03/2011 Document #: 38-07290 Rev. *D Orig. of Description of Change Change BRK New Data Sheet RBI Added power up requirements to Maximum Ratings ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07290 Rev. *D All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised June 3, 2011 CY29972 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...