CY29943 Cypress Semiconductor, CY29943 Datasheet

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CY29943

Manufacturer Part Number
CY29943
Description
1:18 Clock Distribution Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Features
Cypress Semiconductor Corporation
Document #: 38-07285 Rev. *C
• 200-MHz clock support
• 2.5V or 3.3V operation
• LVPECL clock input
• LVCMOS-/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 200 ps max. output-to-output skew
• Output Enable control
• Pin compatible with MPC942P
• Available in Industrial and Commercial
• 32-pin LQFP package
Block Diagram
PECL_CLK
PECL_CLK#
OE
VDD
18
2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer
3901 North First Street
Q0-Q17
Description
The CY29943 is a low-voltage 200-MHz clock distribution
buffer with an LVPECL-compatible input clock. All other control
inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs
are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can
drive 50 series or parallel terminated transmission lines. For
series terminated transmission line, each output can drive one
or two traces giving the device an effective fanout of 1:36. Low
output-to-output skews make the CY29943 an ideal clock
distribution buffer for nested clock trees in the most
demanding of synchronous systems.
PECL_CLK#
PECL_CLK
Pin Configuration
VDD
VDD
VSS
VSS
OE
NC
San Jose
1
2
3
4
5
6
7
8
CY29943
CA 95134
Revised December 21, 2002
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
CY29943
408-943-2600

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CY29943 Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-07285 Rev. *C 2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer Description The CY29943 is a low-voltage 200-MHz clock distribution buffer with an LVPECL-compatible input clock. All other control inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission line, each output can drive one or two traces giving the device an effective fanout of 1:36 ...

Page 2

... Document #: 38-07285 Rev. *C PWR I PECL Input Clock I, PD PECL Input Clock I, PU Output Enable. When HIGH, all the outputs are enabled. When set LOW, the outputs are at high impedance. VDD O Clock Outputs 3.3V or 2.5V Power Supply Common Ground No Connection CY29943 Description Page ...

Page 3

... V ) < out Min. Typ. Max. V 0 –200 200 500 1000 V – 1.4 V – 0 – 1.0 V – 0 0.5 2.4 2 285 335 200 240 CY29943 Unit V V µA µ CMR Page ...

Page 4

... Part-to-Part Skew Tr/Tf Output Clocks Rise/Fall [7, 8] Time Differential Pulse Generator ohm Figure 1. PECL_CLK CY29943 Test Reference for V PECL_CLK PECL_CLK Notes: 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50 transmission lines. 8. ...

Page 5

... Document #: 38-07285 Rev 100% Figure 3. Output Duty Cycle (FoutDC) t SK(0) Figure 4. Output-to-Output Skew tsk(0) CY29943 VCC VCC /2 GND VCC VCC /2 GND VCC VCC /2 GND Page ...

Page 6

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type Industrial, –40°C to +85°C Industrial, –40°C to +85°C Commercial, 0°C to +70°C Commercial, 0°C to +70°C CY29943 Production Flow 51-85088-*B Page ...

Page 7

... Document History Page Document Title: CY29943 2.5V or 3.3V 200-MHz 1:18 Clock Distribution Buffer Document Number: 38-07285 Issue REV. ECN NO. Date ** 111096 02/07/02 *A 116779 08/14/02 *B 118744 09/18/02 *C 122877 12/21/02 Document #: 38-07285 Rev. *C Orig. of Change BRK New data sheet HWT Add Commercial Temperature range in the ordering Information HWT Update output duty cycle on page 4 RBI Add power up requirements to maximum rating information ...

Page 8

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