CY29940 Cypress Semiconductor, CY29940 Datasheet

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CY29940

Manufacturer Part Number
CY29940
Description
2.5V or 3.3V/ 200-MHz/ 1:18 Clock Distribution Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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40
Features
Cypress Semiconductor Corporation
Document #: 38-07283 Rev. *B
• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 150 ps max. output-to-output skew
• Dual or single supply operation:
• Pin compatible with MPC940L, MPC9109
• Available in Commercial and Industrial temperature
• 32-pin LQFP package
Block Diagram
— 3.3V core and 3.3V outputs
— 3.3V core and 2.5V outputs
— 2.5V core and 2.5V outputs
PECL_CLK#
PECL_CLK
TCLK_SEL
TCLK
VDD
0
1
VDDC
2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
3901 North First Street
18
Q0-Q17
Description
The CY29940 is a low-voltage 200-MHz clock distribution buff-
er with the capability to select either a differential LVPECL or
a LVCMOS/LVTTL compatible input clock. The two clock
sources can be used to provide for a test clock as well as the
primary system clock. All other control inputs are LVC-
MOS/LVTTL compatible. The eighteen outputs are 2.5V or
3.3V LVCMOS/LVTTL compatible and can drive 50 series or
parallel terminated transmission lines. For series terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:36. Low out-
put-to-output skews make the CY29940 an ideal clock distri-
bution buffer for nested clock trees in the most demanding of
synchronous systems.
PECL_CLK#
PECL_CLK
TCLK_SEL
Pin Configuration
VDDC
TCLK
VDD
VSS
VSS
San Jose
1
2
3
4
5
6
7
8
CY29940
CA 95134
Revised December 21, 2002
24
23
22
21
20
19
18
17
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
CY29940
408-943-2600

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CY29940 Summary of contents

Page 1

... Document #: 38-07283 Rev. *B 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Description The CY29940 is a low-voltage 200-MHz clock distribution buff- er with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock ...

Page 2

... PECL Input Clock I, PD PECL Input Clock I, PD External Reference/Test Clock Input VDDC O Clock Outputs I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 3.3V or 2.5V Power Supply for Output Clock Buffers 3.3V or 2.5V Power Supply Common Ground CY29940 Description Page ...

Page 3

... A Min. Typ. Max 2.0 V –200 500 1000 V – 1 – 1 3.3V 2.4 DDC = 2.5V 1.8 DDC 5 285 335 200 240 ( VDD/2) transmission lines CY29940 Unit. 0 µA 200 µA mV – 0.6 V – 0 Page ...

Page 4

... Min. Typ. Max. 200 t 2.0 3.2 PHL t 2.1 3.4 PLH t 1.9 3.1 PHL t 2.0 3.2 PLH t 2.5 5.2 PHL t 2.6 5 PLH t 2.5 5 PHL t 2.6 5 PLH t 1.9 3 PHL t 2.0 3.2 PLH t 1.8 2.9 PHL t 1.8 3.1 PLH t 2.5 4 PHL t 2.5 4 PLH t 2.3 3.8 PHL t 2.3 3.8 PLH 150 200 1.4 2.2 1.2 1.7 850 750 0.3 1.1 0.3 1.2 CY29940 Units MHz Page ...

Page 5

... Pulse Generator ohm Figure 1. LVCMOS_CLK CY29940 Test Reference for V Differential Pulse Generator ohm Figure 2. PECL_CLK CY29940 Test Reference for V PECL_CLK V PECL_CLK Figure 3. Propagation Delay (TPD) Test Reference LVCMOS_CLK Figure 4. LVCMOS Propagation Delay (TPD) Test Reference Document #: 38-07283 Rev. *B ...

Page 6

... Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Type Industrial, –40°C to +85°C Industrial, –40°C to +85°C CY29940 Production Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C ...

Page 7

... Document Title: CY29940 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Document Number: 38-07283 Issue REV. ECN NO. Date ** 111094 02/01/02 *A 116776 08/15/02 *B 122875 12/21/02 Document #: 38-07283 Rev. *B Orig. of Change BRK New data sheet HWT Incorporate results of final characterization using corporate methods, added output impedance on page 3 and added output duty cycle on page 4. ...

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