CY29352 Cypress Semiconductor, CY29352 Datasheet

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CY29352

Manufacturer Part Number
CY29352
Description
11 Output Zero Delay Buffer
Manufacturer
Cypress Semiconductor
Datasheet

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Cypress Semiconductor Corporation
Document Number: 38-07476 Rev. *B
Features
Block Diagram
Output frequency range: 16.67 MHz to 200 MHz
Input frequency range: 16.67 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V and 3.3V outputs
±2% maximum output duty cycle variation
11 clock outputs: drive up to 22 clock lines
LVCMOS reference clock input
125 ps maximum output-output skew
PLL bypass mode
Spread Aware™
Output enable and disable
Pin compatible with MPC9352 and MPC952
Industrial temperature range: –40°C to +85°C
32-pin 1.4 mm TQFP package
VCO_SEL
PLL_EN#
REFCLK
MR/OE#
FB_IN
SELC
SELA
SELB
198 Champion Court
Detector
Phase
LPF
200-500MHz
VCO
Description
The CY29352 is a low voltage high performance 200 MHz PLL
based zero delay buffer designed for high speed clock distri-
bution applications.
The CY29352 features an LVCMOS reference clock input and
provides 11 outputs partitioned in three banks of five, four, and
two outputs. Bank A divides the VCO output by four and six
while bank B divides by four and two, and bank C divides by
two and four per SEL(A:C) settings, see
These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1,
2:3, 1:2, and 1:3. Each LVCMOS compatible output drives 50Ω
series or parallel terminated transmission lines. For series
terminated transmission lines, each output drives one or two
traces, giving the device an effective fanout of 1:22.
The PLL is stable if the VCO is configured to run between 200
MHz to 500 MHz. This allows a wide range of output
frequencies from 16.67 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO runs at multiples of the
input reference clock set by the feedback divider, see
on page
reference clock directly feeds the output dividers. This mode
is fully static and the minimum input clock frequency specifi-
cation does not apply.
11 Output Zero Delay Buffer
÷2
3.
When PLL_EN# is HIGH, PLL is bypassed and the
San Jose
÷4 /
÷4 /
÷2 /
÷6
÷2
÷4
2.5V or 3.3V, 200 MHz,
,
CA 95134-1709
QC1
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QC0
Revised January 14, 2008
Table 3
CY29352
408-943-2600
on page 3.
Table 2
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CY29352 Summary of contents

Page 1

... Cypress Semiconductor Corporation Document Number: 38-07476 Rev Output Zero Delay Buffer Description The CY29352 is a low voltage high performance 200 MHz PLL based zero delay buffer designed for high speed clock distri- bution applications. The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in three banks of five, four, and two outputs ...

Page 2

... DD Supply V 2.5V or 3.3V power supply for PLL DD Supply V 2.5V or 3.3V power supply for core and inputs DD Supply Ground Analog ground Supply Ground Common ground CY29352 VSS QB1 QB0 VDDQB VDDQA QA4 QA3 VSS Description Table 3 on page 3. Table 3 on page Table 3 on page 3. ...

Page 3

... SS Relative Functional Ripple frequency < 100 kHz Non functional Functional Functional Functional Functional Manufacturing test CY29352 Input Frequency Range (AVDD = 2.5V) 100 MHz to 200 MHz 50 MHz to 100 MHz 33.33 MHz to 66.67 MHz 50 MHz to 100 MHz 25 MHz to 50 MHz 16.67 MHz to 33.33 MHz 1 VCO ÷ 2 Bypass mode, PLL disabled, the input clock ...

Page 4

... [ – [ only DD All V pins except Alternatively, each output drives up to two 50Ω series terminated transmission TT CY29352 Min Typ Max Unit 0 0.6 V 1.8 V μA –10 μA 100 170 ...

Page 5

... Banks at same voltage, different frequency ÷2 feedback ÷4 feedback ÷6 feedback ÷8 feedback ÷12 feedback Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300 MHz VCO > 300 MHz CY29352 Min Typ Max Unit 200 400 MHz 100 200 MHz 50 100 33 ...

Page 6

... Same frequency Multiple frequencies Same frequency Multiple frequencies VCO < 300 MHz VCO > 300 MHz . Outputs are at the same supply voltage unless otherwise stated. Parameters are guaranteed TT CY29352 Min Typ Max Unit 200 500 MHz 100 200 MHz ...

Page 7

... Figure 4. Output Duty Cycle (DC 100% Figure 5. Output to Output Skew 3. ohm ohm T VTT GND GND GND sk( GND GND t SK(O) CY29352 Page [+] Feedback ...

Page 8

... Ordering Information Part Number Pb-Free CY29352 AXI 32-pin TQFP CY29352 AXIT 32-pin TQFP—tape and reel Package Drawing and Dimension www.DataSheet4U.com Document Number: 38-07476 Rev. *B Package Type Figure 6. 32 Lead Thin Plastic Quad Flatpack 1.4 mm CY29352 Product Flow Industrial, –40°C to +85°C Industrial, – ...

Page 9

... Document History Page Document Title:CY29352 2.5V or 3.3V, 200 MHz, 11 Output Zero Delay Buffer Document Number: 38-07476 REV. ECN No. Issue Date ** 124654 03/21/03 *A 739798 See ECN *B 1923227 See ECN www.DataSheet4U.com © Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

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