CY28441 Cypress Semiconductor, CY28441 Datasheet - Page 11

• Manufacturer Part Number: CY28441
• Description: Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07679 Rev. **
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
CPUC(Free Running
CPUT(Free Running
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running)
CPUT(Free Running)
CPU_STOP#
CPUC(Stoppable)
CPUT(Stoppable)
CPUC Internal
CPUT Internal
CPU_STOP#
CPU_STP#
DOT96C
DOT96T
DOT96T
DOT96C
CPUT
CPUC
PD
PD
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
Figure 9. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z
Figure 7. CPU_STP# Deassertion Waveform
Tdrive_CPU_STP#,10nS>200mV
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
1.8mS
1.8mS
CY28441
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