CY28419 Cypress Semiconductor, CY28419 Datasheet - Page 9

• Manufacturer Part Number: CY28419
• Description: Clock Synthesizer
• Manufacturer: Cypress Semiconductor

Document #: 38-07444 Rev. *D
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms. The
CPUT/C outputs must be driven to greater than 200 mV is less
than 300 us.
CPUC, 133MHz
CPUC, 133MHz
CPUT, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCC 100MHz
SRCT 100MHz
SRCT 100MHz
3V66, 66MHz
3V66, 66MHz
USB, 48MHz
USB, 48MHz
PCI, 33MHz
PCI, 33MHz
REF
REF
PD#
PD#
Figure 4. Power-down Deassertion Timing Waveforms
Figure 3. Power-down Assertion Timing Waveforms
<300µS, >200mV
Tdrive_PWRDN#
<1.8ms
Tstable
CY28419
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