CY28400 Cypress Semiconductor, CY28400 Datasheet - Page 9

• Manufacturer Part Number: CY28400
• Description: 100-MHz Differential Buffer for PCI Express and SATA
• Manufacturer: Cypress Semiconductor

Document #: 38-07591 Rev. **
SRC_DIV2# Deassertion
The impact of writing a ‘0’ to the SRC_DIV/2 register bit is all
DIF outputs will transition cleanly in a glitch-free manner from
divide by 2 mode to normal (output frequency is equal to the
input frequency) operation within 2–6 DIF clock periods.
PLL/BYPASS# Clarification
The PLL/Bypass# input is used to select between bypass
mode (no PLL) and PLL mode. In bypass mode, the input clock
is passed directly to the output stage resulting in 50ps additive
jitter (50 ps + input jitter) on DIF outputs. In the case of PLL
mode, the input clock is pass through a PLL to reduce high
frequency jitter. The BYPASS# mode may be selected in two
ways, via writing a ‘0’ to SMBus register bit or by asserting the
PLL/BYPASS# pin low. In both methods, if the SMBus register
bit has been written low or PLL/BYPASS# pin is low or both,
the device will be configure for BYPASS operation.
HIGH_BW# Clarification
The HIGH_BW# input is used to set the PLL bandwidth. This
mode is intended to minimize PLL peaking when two or more
buffers are cascaded by staggering device bandwidths. The
PLL low bandwidth mode may be selected in two ways, via
writing a ‘0’ to SMBus register bit or by asserting the
HIGH_BW# pin is low or both, the device will be configured for
low bandwidth operation.
CY28400
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