CY28378 Cypress Semiconductor, CY28378 Datasheet - Page 12

• Manufacturer Part Number: CY28378
• Description: FTG for Pentium 4 and Intel 845 Series Chipset
• Manufacturer: Cypress Semiconductor

Document #: 38-07519 Rev. **
Table 7. Maximum Lumped Capacitive Output Loads
Table 8. Group Timing Relationship and Tolerances
PD# (Power-down) Clarification
The PD# (Power Down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
asynchronous function for powering up the system. When PD#
PD# – Assertion
PCI, PCI_F
3V66
48M_24MHz, 48MHz
REF
CPUT/C
CPU_ITP
3V66 to PCI
REF, 14.131818
CPUC, 133MHz
CPUT, 133MHz
AGP, 66MHz
USB, 48MHz
PCI, 33MHz
PWRDWN#
Clock
Typical 2.5 ns
Offset
Figure 2. Power-down Assertion Timing Waveforms
1.5 – 3.5 ns
(or Range)
Tolerance
is low, all clocks are driven to a LOW value and held there and
the VCO and PLLs are also powered down. All clocks are shut
down in a synchronous manner so has not to cause glitches
while transitioning to the low “stopped” state.
See Figure 4
Max Load
Conditions
3V66 leads
20
30
20
30
See Note 2
Units
Notes
pF
pF
pF
pF
pF
CY28378
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