CY25482 Cypress Semiconductor, CY25482 Datasheet - Page 5

• Manufacturer Part Number: CY25482
• Description: (CY25402 - CY25482) Two PLL Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

General Description
2 Configurable PLLs
The CY25402, CY25422, and CY25482 have two programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having two PLLs is that a
single device generates two independent frequencies from a
single crystal.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25402 and CY25422 while just a clock signal for CY25482.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25482
is 2.5 V/3.0 V/3.3 V while that for CY25402 and CY25422 is
1.8 V. This gives user an option for this device to be compatible
for different input clock voltage levels in the system.
V
These devices have programmable power supply options. The
CY25402/CY25482 is a high voltage part that can be
programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while
CY25422 is a low voltage part that can operate at 1.8 V.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are three available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock
source selection is done by using three out of three crossbar
switch. Thus, any one of these three available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have two independent clock outputs.
Spread Spectrum Control
Both PLLs (PLL1 and PLL2) have spread spectrum capability for
EMI reduction in the system. The device uses a Cypress
proprietary PLL and spread spectrum clock (SSC) technology to
synthesize and modulate the frequency of the PLL. The spread
spectrum feature can be turned on or off using a multifunction
control pin (CLK2/SSON). It can be programmed to either center
spread range from ±0.125% to ±2.50% or down spread range
from –0.25% to –5.0% with lexmark or linear profile.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
REFOUT/FS0 and PD#/OE/FS1 which if programmed as
frequency select inputs, can be used to select among these
arbitrarily programmed frequency settings. Each output has
programmable output divider options.
Document #: 001-12565 Rev. *F
DD
Power Supply Options
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched
uninterrupted system operation while clock frequency is being
switched.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values.
typical rise and fall times for different drive strength settings.
Table 5. Output Drive Strength
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY25402, CY25422, and CY25482 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
field application engineer (FAE) or sales representative.
Output Drive Strength
Mid High
Mid Low
using
High
Low
CY25402/CY25422/CY25482
output
dividers.
Table 4
Rise/Fall Time (ns)
(Typical Value)
This
on page 4 shows the
6.8
3.4
2.0
1.0
feature
Page 5 of 14
enables