CY25100 Cypress Semiconductor, CY25100 Datasheet - Page 5

• Manufacturer Part Number: CY25100
• Description: Field- and Factory-Programmable Spread Spectrum Clock Generator for EMI Reduction
• Manufacturer: Cypress Semiconductor

Document #: 38-07499 Rev. *D
AC Electrical Characteristics
Application Circuit
DC
SR1
SR2
SR3
SR4
T
T
T
t
T
T
t
t
2. Jitter is configuration dependent. Actual jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, spread percentage, temper-
3. Since the load capacitors (C
4. If an external clock is used, apply the clock to XIN (pin 3) and leave XOUT (pin 2) floating (unconnected).
5. If SSON# (pin 8) is LOW (V
Parameter
STP
PU1
PU2
CCJ1
CCJ2
CCJ3
OE1
OE2
ature, and output load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at
http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer.
capacitor (C
[2]
[2]
[2]
L
). Only a single 0.1-µF bypass capacitor is required on the V
Output Duty Cycle
Output Duty Cycle
Rising Edge Slew Rate
Falling Edge Slew Rate
Rising Edge Slew Rate
Falling Edge Slew Rate
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
Cycle-to-Cycle Jitter
SSCLK (Pin 7)
Cycle-to-Cycle Jitter
REFCLK (Pin 6)
Power-down Time
(pin 4 = PD#)
Output Disable Time
(pin 4 = OE)
Output Enable Time
(pin 4 = OE)
Power-up Time,
Crystal is used
Power-up Time,
Reference clock is used
Description
SS
[3, 4, 5]
XIN
), the frequency modulation will be on at SSCLK pin (pin 7).
and C
XOUT
P o w e r
) are provided by the CY25100, no external capacitors are needed on the XIN and XOUT pins to match the crystal load
[1]
0 . 1 u F
SSCLK, Measured at V
REFCLK, Measured at V
Duty Cycle of CLKIN = 50% at input bias
SSCLK from 3 to 100 MHz; REFCLK from 3 to 100
MHz. 20%–80% of V
SSCLK from 3 to 100 MHz; REFCLK from 3 to 100
MHz. 80%–20% of V
SSCLK from 100 to 200 MHz; REFCLK from 100 to
166 MHz 20%–80% of V
SSCLK from 100 to 200 MHz; REFCLK from 100 to
166 MHz 80%–20% of V
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK off
CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK off
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK off
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 166 MHz, 2% spread, REFCLK on
CLKIN = SSCLK = 66 MHz, 2% spread REFCLK on
CLKIN = SSCLK = 33 MHz, 2% spread, REFCLK on
Time from falling edge on PD# to stopped outputs
(Asynchronous)
Time from falling edge on OE to stopped outputs
(Asynchronous)
Time from rising edge on OE to outputs at a valid fre-
quency (Asynchronous)
Time from rising edge on PD# to outputs at valid fre-
quency (Asynchronous)
Time from rising edge on PD# to outputs at valid fre-
quency (Asynchronous), reference clock at correct
frequency
V D D
1
2
3
4
P D # / O E
V D D
X I N / C L K I N
X O U T
DD
C Y 2 5 1 0 0
pin.
DD
DD
Condition
DD
DD
DD
DD
/2
/2
R E F C L K
S S C L K
S S O N #
V S S
8
7
6
5
Min.
0.7
0.7
1.2
1.2
45
40
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Typ.
100
130
100
105
200
100
135
150
150
150
1.1
1.1
1.6
1.6
3.5
90
80
50
50
2
CY25100
Max.
120
130
170
130
140
260
100
130
180
350
350
350
Page 5 of 11
3.6
3.6
4.0
4.0
55
60
5
3
Unit
V/ns
V/ns
V/ns
V/ns
ms
ms
ps
ps
ps
ns
ns
ns
ps
ps
ps
ps
ps
ps
%
%