CY25000 Cypress Semiconductor, CY25000 Datasheet - Page 4

• Manufacturer Part Number: CY25000
• Description: Programmable Spread Spectrum Clock Generator
• Manufacturer: Cypress Semiconductor

Document #: 38-07424 Rev. *B
AC Electrical Characteristics
Table 1.
Programming Description
The customers planning to use the CY25000 need to provide
the programming information described as “ENTER DATA” in
Table 1 and should contact local Cypress Sales.
Additional information on the CY25000 can be obtained from
the Cypress web site at www.cypress.com.
Product Functions
Input Frequency (XIN, pin 1 and XOUT
The input to the CY25000 can be a crystal or a clock. The input
frequency range for crystals is 8 to 30 MHz, and for clock
signal is 8 to 166 MHz.
C
The load capacitors at pin 1 (C
programmed from 12 pF to 60 pF with 0.5-pF increments. The
programmed value of these on-chip crystal load capacitors are
the same (XIN = XOUT = 12 to 60 pF).
The required values of C
using the following formula:
SR3
SR4
tj1
tj2
t
T
T
t
t
STP
PU1
PU2
XIN
OE1
OE2
PROGRAM
Pin Name
Function
Parameter
VALUE
Units
and C
Pin#
Pin
XOUT
XIN and XOUT
(pin 1 and pin 8)
ENTER DATA
Rising Edge Slew Rate
Falling Edge Slew Rate
Peak Cycle-to-Cycle Jitter.
SSCLK pin
Peak Cycle-to-Cycle Jitter,
REFCLK
Power-down Time
(pin3 = PD#)
Output Disable Time
(pin3 = OE)
Output Enable Time
(pin3 = OE)
Power-up Time,
Crystal is used
Power-up Time,
Reference clock is used
Frequency
1 and 8
Input
MHz
XIN
Description
and C
XIN
) and pin 8 (C
ENTER DATA ENTER DATA
C
XOUT
XIN and
1 and 8
[1]
C
XOUT
XIN
XOUT
pF
,
pin 8)
and
can be calculated
SSCLK from 100 to 200 MHz; REFCLK
from 100 to 166 MHz 20%–80% of V
SSCLK from 100 to 200 MHz; REFCLK
from 100 to 166 MHz 80%–20% of V
SSCLK = 200 MHz. Spread on
SSCLK = 66 MHz. Spread on
SSCLK = 14.3 MHz. Spread on
REFCLK output only
Time from falling edge on PD# to stopped
outputs (Asynchronous)
Time from falling edge on OE to stopped
outputs (Asynchronous)
Time from rising edge on OE to outputs at
a valid frequency (Asynchronous)
Time from rising edge on PD# to outputs
at valid frequency (Asynchronous)
Time from rising edge on PD# to outputs
at valid frequency (Asynchronous)
XOUT
Frequency
) can be
Output
SSCLK
MHz
5
Condition
C
Where C
crystal manufacturer and C
For example, if a fundamental 16-MHz crystal with C
is used and C
C
If using a driven reference, set C
minimum value 12 pF.
Output Frequency, SSCLK Output (SSCLK, pin 5)
The modulated frequency at the SSCLK output is produced by
synthesizing the input reference clock. The modulation can be
stopped by SSON digital control input (SSON = LOW, no
modulation). If modulation is stopped, the clock frequency is
the nominal value of the synthesized frequency without
modulation (spread % = 0). The range of synthesized clock is
from 3–200 MHz.
Spread Percentage (SSCLK, pin 5)
The SSCLK frequency can be programmed at any percentage
value from ±0.25% to ±2.5% for Center Spread and from
–0.5% to –5.0% Down Spread.
Percent
Spread
ENTER
SSCLK
XIN
XIN
DATA
%
5
= C
= C
XOUT
XOUT
L
is the crystal load capacitor as specified by the
ENTER DATA
Reference
P
= (2 x 16) – 2 = 30 pF.
REFOUT
On or Off
= 2C
Output
is 2 pF, C
6
DD
DD
L
- C
P
XIN
Min.
P
1.2
1.2
Select PD# or OE
Power-down or
and C
is the parasitic PCB capacitance.
Output Enable
ENTER DATA
PD#/OE
XOUT
3
Typ.
100
150
200
100
150
150
150
1.6
1.6
XIN
3
2
can be calculated as:
and C
CY25000
Max.
300
400
200
200
300
300
300
2.0
2.0
5
3
Page 4 of 10
Modulation
Frequency
XOUT
SSCLK
L
kHz
30
of 16 pF
5
Unit
V/ns
V/ns
to the
ms
ms
ps
ps
ps
ns
ns
ns
ps