CY24293 Cypress Semiconductor, CY24293 Datasheet - Page 3

• Manufacturer Part Number: CY24293
• Description: Two Outputs PCI-Express Clock Generator
• Manufacturer: Cypress Semiconductor

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Application Information
Crystal Recommendations
CY24293 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24293 to operate at the wrong
frequency and violate the ppm specification. For most applications, there is a 300 ppm frequency shift between series and parallel
crystals due to incorrect loading.
Table 4. Crystal Recommendations
Crystal Loading
Crystal loading plays a critical role in achieving low ppm
performance. To realize low ppm performance, consider the total
capacitance the crystal sees to calculate the appropriate
capacitive loading (CL).
Figure 2
capacitors. It is important to note that the trim capacitors in series
with the crystal are not parallel. It is a common misconception
that load capacitors are in parallel with the crystal and must be
approximately equal to the load capacitance of the crystal. This
is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading.
As mentioned in the previous section, the capacitance on each
side of the crystal is in series with the crystal. This means the
total capacitance on each side of the crystal must be twice the
specified crystal load capacitance (CL). While the capacitance
on each side of the crystal is in series with the crystal, trim
capacitors (Ce1, Ce2) must be calculated to provide equal
capacitive loading on both sides.
Figure 2. Crystal Loading Example
Document Number: 001-46117 Rev. *C
Cs1
Frequency
25.00 MHz
Ce1
shows a typical crystal configuration using two trim
X1
Ci1
Clock Chip
XTAL
Parallel
Cut
Ci2
X2
Ce2
Load Cap
16 pF
Cs2
3 to 6p
Pin
Trim
26 pF
Trace
2.8 pF
Eff Series Rest
(max)
30 Ω
Drive (max)
Use the following formulas to calculate the trim capacitor values
for Ce1 and Ce2:
CL ................................................... Crystal load capacitance
CLe......................................... Actual loading seen by crystal
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
Current Source (Iref) Reference Resistor
If the board target trace impedance (Z) is 50Ω, then for
R
current (I
Output Termination
The PCI-Express differential clock outputs of the CY24293 are
open source drivers and require an external series resistor and
a resistor to ground. These resistor values and their allowable
locations are explained in the section
Guidelines
LVDS compatible voltage levels. Refer to the section
Compatible Layout Guidelines
1.0 mW
REF
CLe
= 475Ω (1%), provides IREF of 2.32 mA. The output
OH
Total capacitance (as seen by the crystal)
=
on page 4. The CY24293 can also be configured for
) is equal to 6*IREF.
Tolerance (max) Stability (max) Aging (max)
(
Load capacitance (each side)
Ce1 + Cs1 + Ci1
30 ppm
Ce = 2 * CL – (Cs + Ci)
1
using standard value trim capacitors
on page 5.
+
1
Ce2 + Cs2 + Ci2
10 ppm
PCI-Express Layout
1
CY24293
Page 3 of 10
5 ppm/yr.
)
LVDS
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