CY24239 Cypress Semiconductor, CY24239 Datasheet
CY24239
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CY24239 Summary of contents
Page 1
... Clock Control CPU2 VDDQ3 PCI_F/MODE PCI0/FS3 PCI1 Stop Clock PCI2 Control PCI3 PCI4 PCI5 VDDQ3 Note: 48MHz/FS1 1. 24MHz/FS0 VDDQ3 SDRAM0:16 17 • 3901 North First Street CY24239 Input Address CPU_F, PCI_F, CPU1:2 PCI0:5 FS2 FS1 FS0 (MHz) (MHz 91.66 30 75.0 25 100 ...
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... Power Connection: Power supply for core logic, PLL circuitry, SDRAM output buffers, PCI output buffers, reference output buffers and 48-MHz/24-MHz output buffers. Con- nect to 3.3V. G Ground Connections: Connect all ground pins to the common system ground plane. CY24239 Pin Description Page ...
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... DD Figure 2 show two suggested methods for strapping resistor connections. Upon CY24239 power-up, the first operation is used for input logic selection. During this period, the five I/O pins ( 29, 30) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “ ...
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... Sales representative for details on these devices. Spread Spectrum clocking is activated or deactivated by se- (F) lecting the appropriate values for bits 1–0 in data byte 0 of the 10 SMBus data stream. Refer to Table 7 for more details. EMI Reduction Spread Enabled Figure 4. Typical Modulation Profile CY24239 Non- Spread Spectrum Page ...
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... Refer to Table 5 The data bits in Data Bytes 0–7 set internal CY24239 registers that control device operation. The data bits are only accepted when the Ad- dress Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map ...
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... Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable Clock Output Disable -- (Reserved) -- (Reserved) Clock Output Disable Clock Output Disable Clock Output Disable CY24239 Bit Control Refer to Table 6 Refer to Table 6 Refer to Table 6 Frequency Con- Frequency Con- trolled by FS(3:0) Ta- ...
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... Clock Output Disable -- (Reserved) -- (Reserved) -- (Reserved) -- (Reserved) -- (Reserved) -- (Reserved) -- (Reserved) -- (Reserved) -- (Reserved) -- (Reserved) Disabled Disabled -- (Reserved) -- (Reserved) Clock Output Disable Clock Output Disable CY24239 Bit Control 0 1 Default LOW Active LOW Active LOW Active -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ...
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... PCI Clocks (MHz) Percentage 91.66 30.5 75.0 25.0 100.0 33.3 83.3 27.76 66.6 33.3 105.0 26.3 110.0 27.5 133.3 33.3 91.66 30.5 75.0 25.0 100.0 33.3 83.3 27.76 91.66 30.5 75.0 25.0 100.0 33.3 83.3 27.76 Output Conditions PCI_F, REF0:1, PCI0:5 IOAPIC0,_F 48MHZ Note 2 14.318 MHz 48 MHz Hi-Z Hi-Z Hi-Z CY24239 OFF OFF OFF OFF OFF OFF OFF OFF –1.2% –1.2% –1.2% –1.2% –2.4% –2.4% –2.4% –2.4% 24MHZ 24 MHz Hi-Z Page ...
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... All clock outputs loaded with 6" 60 transmission lines with 22-pF capacitors. 4. CY24239 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device. Document #: 38-07038 Rev. ** above those specified in the operating sections of this specifi- cation is not implied ...
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... X1 input threshold voltage (typical The CY24239 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 20 pF; this includes typical stray capacitance of short PCB traces to crystal input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). ...
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... Measured from 0.4V to 2.4V Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Average value during switching transition. Used for determining series termination value. CY24239 Min. Typ. Max. Unit ...
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... Measured from 2.4V to 0.4V Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. Average value during switching transition. Used for determining series termination value. CY24239 SDRAMIN = 100 MHz Min. Typ. Max. Unit 10 10 ...
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... Measured on rising and falling edge at 1.5V Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to fre- quency stabilization. Average value during switching transition. Used for determining series termination value. Package Type CY24239 Min. Typ. Max. Unit 24.004 MHz ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 56-Pin Small Shrink Outline Package (SSOP, 300 mils) CY24239 Page ...
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... Document Title:CY24239 Spread Spectrum Frequency Timing Generator Document Number:38-07038 REV. ECN NO. ** 106975 Document #: 38-07038 Rev. ** Issue Date Orig. of Change 05/24/01 IKA CY24239 Description of Change New Data Sheet Page ...