CY23FS08 Cypress Semiconductor, CY23FS08 Datasheet - Page 4

• Manufacturer Part Number: CY23FS08
• Description: Failsafe 2.5 V/3.3 V Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

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Table 2. Configuration Table (continued)
FailSafe Function
The CY23FS08 is targeted at clock distribution applications that
requires or may require continued operation if the main reference
clock fails. Existing approaches to this requirement have used
multiple reference clocks with either internal or external methods
to switch between references. The problem with this technique
is that it leads to interruptions (or glitches) when transitioning
from one reference to another, often requiring complex external
circuitry or software to maintain system stability. The technique
implemented in this design completely eliminates any switching
of references to the PLL, greatly simplifying system design.
The CY23FS08 PLL is driven by the crystal oscillator, which is
phase-aligned to an external reference clock so that the output
of the device is effectively phase-aligned to reference via the
external feedback loop. This is accomplished by using a digitally
Document Number: 38-07518 Rev. *F
S[4:1]
O U T
0101
1001
0001
0100
1010
0010
1011
0011
1100
0110
1101
0111
1111
R E F
F A I L # / S A F E
8.50
8.33
8.33
8.33
8.00
8.00
8.33
8.33
8.33
8.33
8.33
8.33
8.33
Min
XTAL (MHz)
Max
30
30
30
30
25
25
30
30
30
30
30
30
30
Figure 2. Fail#/Safe Timing for Input Reference Failing Catastrophically
t
F S L
25.00
32.00
64.00
16.67
12.50
6.80
2.78
8.33
1.04
4.17
4.17
1.39
6.25
Min
REF(MHz)
100.00
200.00
24.00
90.00
10.00
30.00
15.00
60.00
15.00
45.00
22.50
Max
3.75
5.00
32.00
64.00
33.33
16.67
50.00
50.00
11.11
1.70
6.25
2.78
8.33
2.08
8.33
Min
controlled capacitor array to pull the crystal frequency over an
approximate range of ±300 ppm from its nominal frequency.
In this mode, if the reference frequency fails (that is, stops or
disappears), the DCXO maintains its last setting and a flag signal
(FAIL#/SAFE) is set to indicate failure of the reference clock.
The CY23FS08 provides four select bits, S1 through S4 to
control the reference to crystal frequency ratio. The DCXO is
internally tuned to the phase and frequency of the external
reference only when the reference frequency divided by this ratio
is within the DCXO capture range. If the frequency is out of
range, a flag is set on the FAIL#/SAFE pin notifying the system
that the selected reference is not valid. If the reference moves in
range, then the flag is cleared, indicating to the system that the
selected reference is valid.
OUT(MHz)
100.00
200.00
120.00
180.00
180.00
22.50
10.00
30.00
30.00
60.00
40.00
Max
6.00
7.50
REF:OUT
Ratio
4
4
×1
×1
×1
×1
×2
×2
×2
×4
×4
×8
×8
t
F S H
REF:XTAL
Ratio
4/5
1/3
1/8
1/2
1/2
3/2
1/6
3/4
3
1
4
8
2
CY23FS08
Out:XTAL Ratio
Page 4 of 15
1/5
3/4
1/3
1/4
4/3
1
4
8
1
4
2
6
6
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