CY23EP05 Cypress Semiconductor, CY23EP05 Datasheet - Page 2

• Manufacturer Part Number: CY23EP05
• Description: 5 Output Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

Document #: 38-07759 Rev. *B
Pin Description
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay.
The output driving the CLKOUT pin will be driving a total load
of 5 pF plus any additional load externally connected to this
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Pin
1
2
3
4
5
6
7
8
REF
CLK2
CLK1
GND
CLK3
V
CLK4
CLKOUT
DD
[1]
[2]
[2]
[2]
[2]
Signal
[2,3]
Input reference frequency
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V or 2.5V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
pin. For applications requiring zero input-output delay, the total
load on each output pin (including CLKOUT) must be the
same. If input-output delay adjustments are required, the
CLKOUT load may be changed to vary the delay between the
REF input and remaining outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
titled “CY2305 and CY2309 as PCI and SDRAM Buffers”.
Description
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CY23EP05
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