CY2308 Cypress Semiconductor, CY2308 Datasheet - Page 2

• Manufacturer Part Number: CY2308
• Description: 3.3V Zero Delay Buffer
• Manufacturer: Cypress Semiconductor

Pin Description
Select Input Decoding
Available CY2308 Configurations
Notes:
Document #: 38-07146 Rev. *C
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
CY2308–1
CY2308–1H
CY2308–2
CY2308–2
CY2308–3
CY2308–3
CY2308–4
CY2308–5H
Pin
S2
10
12
13
14
15
16
11
0
0
1
1
1
2
3
4
5
6
7
8
9
Device
REF
CLKA1
CLKA2
V
GND
CLKB1
CLKB2
S2
S1
CLKB3
CLKB4
GND
V
CLKA3
CLKA4
FBK
DD
DD
[3]
[3]
S1
[1]
0
1
0
1
[2]
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Signal
Feedback From
CLOCK A1–A4
Three-State
Driven
Driven
Driven
Input reference frequency, 5V tolerant input
Clock output, Bank A
Clock output, Bank A
3.3V supply
Ground
Clock output, Bank B
Clock output, Bank B
Select input, bit 2
Select input, bit 1
Clock output, Bank B
Clock output, Bank B
Ground
3.3V supply
Clock output, Bank A
Clock output, Bank A
PLL feedback input
[4]
Reference
Reference
Reference
2 X Reference
2 X Reference
4 X Reference
2 X Reference
Reference /2
CLOCK B1–B4
Bank A Frequency
Three-State
Three-State
Driven
Driven
[4]
Description
Output Source
Reference
PLL
PLL
PLL
Reference
Reference
Reference/2
Reference
Reference or Reference
2 X Reference
2 X Reference
Reference /2
Bank B Frequency
PLL Shutdown
[5]
CY2308
N
N
Y
Y
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