CY22M1 Cypress Semiconductor, CY22M1 Datasheet - Page 3

• Manufacturer Part Number: CY22M1
• Description: Low Power Programmable Clock Generator
• Manufacturer: Cypress Semiconductor

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Functional Description
The MoBL
accuracy, PLL-based clock generator device designed for low
power, space constrained applications. The low jitter and
accurate outputs makes this device suitable for handsets,
portable media players, personal navigation devices, digital
cameras, digital camcorders, and other portable applications.
The device has several programmable options listed in the
section
The entire configuration is one time programmable.
Configurable PLL
The device uses a programmable PLL to generate output
frequencies from 1 to 80 MHz. The high resolution of the PLL and
flexible output dividers provide this flexibility.
Input Reference Clock Option
There is an option of a crystal or clock signal for the input
reference clock. The frequency range for crystal (XIN) is 8 MHz
to 48 MHz, while the range for an external reference clock
(CLKIN) is 1 MHz to 80 MHz. A PLL bypass mode enables this
device to be used as a crystal oscillator.
Multiple VDD Power Supply Option
The device has programmable power supply options. The
operating supply voltages are 2.5V, 3.0V, or 3.3V for CY22M1S
and 1.8V for CY22M1L.
Programmable Output Drive Strength
The DC drive strength of the clock output can be programmed to
one of two settings, enabling control of output rise and fall times.
Table 2
strength settings.
Table 2. Output Drive Strength
Document Number: 001-49075 Rev. *C
Output Drive Strength
Programmable Features
shows the typical rise and fall times for both of the drive
®
High
Low
UniClock CY22M1 is a programmable, high
on page 4 of this data sheet.
Rise/Fall Time (ns)
(Typical Value)
2.0
1.0
PRELIMINARY
Power Management Feature
The MoBL
(active HIGH) functions. When the power down mode is selected
(PD# =0), the oscillator and PLL are placed in a low supply
current standby mode and the output is tristated and weakly
pulled LOW. The oscillator and PLL circuits must relock when the
part exits the power down mode. If the output is disabled (OE=0),
the output is tristated and weakly pulled LOW. In this mode, the
oscillator and PLL circuits continue to operate, which enables a
rapid return to normal operation when the output is enabled.
I n addition, the PD# or OE mode can be programmed to occur
asynchronously or synchronously with respect to the output
signal. When the asynchronous setting is used, entering power
down or disabling the output occurs immediately (enabling logic
delays) regardless of the position in the clock cycle. Similarly,
exiting power down or enabling the output occurs immediately
with no guarantee of full output clock pulses. However, when the
synchronous setting is used, the part waits for a falling edge at
the output before entering power down or disabling the output.
This prevents output glitches. The first output pulse is
guaranteed to be a full clock pulse when enabling outputs with a
synchronous OE pin. The first output pulse is not guaranteed to
be a full clock when exiting power down in synchronous or
asynchronous mode.
Output Frequency Tuning
The MoBL
with a built-in programmable capacitor array for fine tuning of the
output frequency. The capacitive load seen by the crystal is
adjusted by programming the memory bits. This feature can
compensate for crystal variations or provide a more accurate
synthesized frequency.
oscillator tuning circuit block diagram.
®
®
UniClock CY22M1 offers PD# (active LOW) and OE
UniClock CY22M1 contains an on-chip oscillator
MoBL
Figure 2
®
on page 4 shows the crystal
UniClock CY22M1
Page 3 of 12
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