AN1934 Freescale Semiconductor / Motorola, AN1934 Datasheet - Page 7

• Manufacturer Part Number: AN1934
• Description: Effects of Skew and Jitter on Clock Tree Design
• Manufacturer: Freescale Semiconductor / Motorola

there is zero output–to–output skew and zero jitter. With zero
skew between the outputs of the MC100EP111, the signals 1a
and 1b are identical. The waveform at point 2 is delayed due to
propagation delay, t
associated with the backplane or cable distribution. By using
the MPC961P zero–delay buffer and placing the appropriate
trace delay in the feedback path of the PLL, we can
compensate for the backplane trace and bring the waveform for
points 5 and 6 back in line with the output of the MC100EP223.
output skew on the MC100EP111, the MC100EP223, and the
phase jitter for the MPC961. (See Figure 14.)
MOTOROLA
The first analysis of the clock tree is with the assumption that
The waveform at point 3 is delayed due to the delay
Next, we will do the same analysis but we will include the
Figure 13. Example Clock Tree Analysis
without Jitter and Skew
pd
, of the MC100EP223.
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We will assume that the output connected to the MC100EP223
is the slowest and thus the longest delay output and that the
output connected through the delay line to the input of the
MPC961C is the fastest or shortest delay output. This analysis
must also be done for the opposite situation; where the
MPC961P is connected to the slowest output and the
MC100EP223 is connected to the fastest output.
propagation delay, t
13. However, by including the output–to–output skew for the
MC100EP223, we find uncertainty in the location of point 2 as
shown in the waveform of point 2 of Figure 14.
MPC961P. Point 4 is the feedback input to the MPC961P and,
in the ideal case, is exactly the same as point 3. However, in this
situation, we have the uncertainty caused by the combination
of the static phase offset, t
MPC961P. Figure 14 depicts these two values added together.
The waveform of point 5 now moves back in time due to the
delay line in the feedback path of the PLL such that the nominal
output now coincides with the HSTL outputs of point 2. Point 6
shows the added uncertainty of the outputs due to the
Initially, we have the output–to–output skew for the EP111.
The waveform at point 2 is delayed from point 1a by the
Point 3 shows the waveform arriving at the input to the
Figure 14. Example Clock Tree Analysis
pd
with Jitter and Skew
, of the MC100EP223 as we had in Figure
(φ)
and the phase jitter for the
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