DS2482-100 Dallas Semiconducotr, DS2482-100 Datasheet - Page 8

• Manufacturer Part Number: DS2482-100
• Description: Single-Channel 1-Wire Master
• Manufacturer: Dallas Semiconducotr

DS2482-100: Single-Channel 1-Wire Master
1-Wire Busy (1WB)
The 1WB bit reports to the host processor whether the 1-Wire line is busy. During 1-Wire communication 1WB is 1;
once the command is completed, 1WB returns to its default 0. Details on when 1WB changes state and for how
long it remains at 1 are found in the Function Commands section.
Presence-Pulse Detect (PPD)
The PPD bit is updated with every 1-Wire Reset command. If the DS2482 detects a presence pulse from a 1-Wire
device at t
during the Presence Detect cycle, the PPD bit will be set to 1. This bit returns to its default 0 if there
MSP
is no presence pulse or if the 1-Wire line is shorted during a subsequent 1-Wire Reset command.
Short Detected (SD)
The SD bit is updated with every 1-Wire Reset command. If the DS2482 detects a logic 0 on the 1-Wire line at t
SI
during the Presence Detect cycle, the SD bit is set to 1. This bit returns to its default 0 with a subsequent 1-Wire
Reset command provided that the short has been removed. If SD is 1, PPD is 0. The DS2482 cannot distinguish
between a short and a DS1994 or DS2404 signaling a 1-Wire interrupt. For this reason, if a DS2404/DS1994 is
used in the application, the interrupt function must be disabled. The interrupt signaling is explained in the
respective device data sheets.
Logic Level (LL)
The LL bit reports the logic state of the active 1-Wire line without initiating any 1-Wire communication. The 1-Wire
line is sampled for this purpose every time the Status register is read. The sampling and updating of the LL bit
takes place when the host processor has addressed the DS2482 in read mode (during the acknowledge cycle),
provided that the Read Pointer is positioned at the Status register.
Device Reset (RST)
If the RST bit is 1, the DS2482 has performed an internal reset cycle, either caused by a power-on reset or from
executing the Device Reset command. The RST bit is cleared automatically when the DS2482 executes a Write
Configuration command to restore the selection of the desired 1-Wire features.
Single Bit Result (SBR)
The SBR bit reports the logic state of the active 1-Wire line sampled at t
of a 1-Wire Single Bit command or the
MSR
first bit of a 1-Wire Triplet command. The power-on default of SBR is 0. If the 1-Wire Single Bit command sends a
0-bit, SBR should be 0. With a 1-Wire Triplet command, SBR could be 0 as well as 1, depending on the response
of the 1-Wire devices connected. The same result applies to a 1-Wire Single Bit command that sends a 1-bit.
Triplet Second Bit (TSB)
The TSB bit reports the logic state of the active 1-Wire line sampled at t
of the second bit of a 1-Wire Triplet
MSR
command. The power-on default of TSB is 0. This bit is updated only with a 1-Wire Triplet command and has no
function with other commands.
Branch Direction taken (DIR)
Whenever a 1-Write Triplet command is executed, this bit reports to the host processor the search direction that
rd
was chosen by the 3
bit of the triplet. The power-on default of DIR is 0. This bit is updated only with a 1-Wire
Triplet command and has no function with other commands. For additional information see the description of the
1-Wire Triplet command and the Dallas Application Note 187, "1-Wire Search Algorithm".
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