UPD78323 NEC, UPD78323 Datasheet - Page 20

• Manufacturer Part Number: UPD78323
• Description: 16/8-BIT SINGLE-CHIP MICROCONTROLLER
• Manufacturer: NEC

20
2.2.1
and modification of operand addressing. They consist of three 16-bit registers and one 8-bit register.
(1) Program counter (PC)
according to the number of bytes of the instruction to be fetched. If an instruction with data branch is executed, immediate
data and the register content are set. RESET input sets and branches the data of 0000H and 0001H reset vector tables
in the PC.
(2) Program status word (PSW)
write access is carried out in units of the higher 8 bits (PSWH) or lower 8 bits (PSWL). Each flag can be operated using
the bit operation instruction. If an interrupt request is made or BRK instruction is executed, data is automatically saved in
the stack and is recovered by RETI or RETB instruction.
The control registers carry out dedicated functions such as control of the program sequence, status and stack memory,
This is a 16-bit register which holds the address information of the next program to be executed. It is normally incremented
This is a 16-bit register consisting of various flags which are set or reset by the result of instruction execution. Read/
All bits are reset to 0 by RESET input.
(a) Interrupt priority level transition flag (LT)
(b) Carry flag (CY)
(c) Zero flag (Z)
(d) Sign flag (S)
(e) Parity/overflow flag (P/V)
not be operated by a program.
into bit 7 or 15, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested by the conditional
branch instruction.
by the conditional branch instruction.
can be tested by the conditional branch instruction.
instruction, this flag is set to 1. In all other cases, it is reset to 0 (overflow flag operation).
is set to 1. If the bit number is odd, this flag is reset to 0 (parity flag operation).
Control Register
This flag is used to control the interrupt priority. For normal operation of the interrupt control circuit, this bit must
If a carry is generated out of bit 7 or 15 as a result of the execution of an operation instruction or a borrow is generated
When a bit control instruction is executed, this flag functions as a bit accumulator.
When the operation result is zero, this flag is set to 1. In all other cases, this flag is reset to 0. This flag can be tested
When MSB of the operation result is “1”, this flag is set to 1. When the MSB is “0”, this flag is reset to 0. This flag
Only when an overflow or underflow occurs as two’s complement during execution of an arithmetic operation
If the bit number of the operation result set to 1 is even during execution of an logic operation instruction, this flag
This flag can be tested by the conditional branch instruction.
PSWH
PSWL
UF
7
7
S
RBS2 RBS1 RBS0
6
Z
6
Figure 2-3. PSW Format
RSS
5
5
AC
4
4
IE
3
0
3
P/V
2
0
2
LT
1
1
0
CY
0
0
0
PD78323, 78324