UPD77111 NEC, UPD77111 Datasheet - Page 23

• Manufacturer Part Number: UPD77111
• Description: 16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS
• Manufacturer: NEC

2.4.4 Wait cycle register
advance by using a register (DWTR)
3. CLOCK GENERATOR
supplies the generated clock to the internal units of the DSP.
Settings related to clock control.
4. RESET FUNCTION
4.1 Hardware Reset
If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed
according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the
instruction at address 0x200 of instruction memory (reset entry).
the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating
voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized.
The number of wait cycles to be inserted when the external data memory area is accessed can be specified in
Note This function is not available on the PD77111 because this DSP does not have an external data area.
The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and
For details of how to set the PLL multiple, refer to 4.2 Initializing PLL, 8.1 Clock Control Options, and 8.3.1
When a low level of a specified width is input to the RESET pin, the device is initialized.
If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized.
On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with
CLKOUT
CLKIN
PLL control circuit
Stop mode
Note
. The number of wait cycles that can be set is 1, 3, or 7.
m
Data Sheet U12801EJ4V0DS00
Output divider
n
Halt divider
Halt mode
PD77110, 77111, 77112
l
Internal
system clock
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