UPD77019-013 NEC, UPD77019-013 Datasheet - Page 18

• Manufacturer Part Number: UPD77019-013
• Description: 16 bits/ Fixed-point Digital Signal Processor
• Manufacturer: NEC

18
2.3.2 MAC: Multiply ACcumulator
data.
unsigned data
2.3.3 ALU: Arithmetic Logic Unit
2.3.4 BSFT: Barrel ShiFTer
operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in MSB first.
2.3.5 SAC: Shifter And Count Circuit
data. Then, bit 39 to bit 5 of output data is always 0.
(2) General register used as 32 bits register
(3) General register used as 24 bits register
(4) General register used as 16 bits register
(5) General register used as 8 bits register
MAC multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. MAC outputs 40 bits
MAC operates three types of multiplication: signed data
Result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right.
ALU performs arithmetic operation and logic operation. Both input/output data are 40 bits.
BSFT performs shift right/left operation. Both input/output data are 40 bits. There are two types of shift right
SAC calculates and outputs shift value for normalization. SAC is input 32 bits data and outputs the 40 bits
Bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent
instruction.
Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended
sign for a load/store instruction.
Bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims.
(a) Signed operand for multiplier
(b) Source/destination for load/store instruction
Bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims.
(c) Unsigned operand for multiplier
(d) Shift value for shift instruction
(e) Source/destination for load/store instruction
(f) Source/destination for inter-register transfer instruction
(g) Destination for immediate data set instruction
(f) Hardware loop times
Bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/
store instruction.
unsigned data.
Preliminary Data Sheet
signed data, signed data
unsigned data and
PD77019-013