AN1250 STMicroelectronics, AN1250 Datasheet - Page 6
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AN1250
Manufacturer Part Number
AN1250
Description
STA014/STA015 MPEG LAYER III DECODER AND ADPCM CODEC
Manufacturer
STMicroelectronics
Datasheet
1.AN1250.pdf
(21 pages)
AN1250 APPLICATION NOTE
The interrupt pulse length may be programmed up to 128 DSP clock cycles using the ADPCM_INT_CFG (0xBE)
register. The polarity of the interrupt signal can be programmed as well. For IRQ pin assignment refer to Figure
5.
Table 4. Mode 2 (G721, 16kHz, 8 bit mono) configuration
3.4 Mode 3 (from SDI to GPSO)
Figure 6. Mode 3 block diagram
Configuring the device in mode 3 incoming data are feed via SDI interface and encoded data are retrieved via
GPSO interface. Since the SDI input interface is not well suited to receive a stereo signal only mono encoding
is supported.
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Address
187
192
184
114
16
83
77
19
MCU
SDI (for decoding)
GPSO_SCKR
GPSO_DATA
GPSO_REQ
ADPCM_SAMPLE_FREQ
ADPCM_CONFIG
SOFT_RESET
ADC_ENABLE
CHIP_MODE
ADC_WLEN
Name
PALY
RUN
STA015
LFBGA64
TQFP44
LRCKT
SCKT
OCLK
SDO
D00AU1186
2 (encoder mode)
3 (decoder mode)
0 (encoder mode)
1 (decoder mode)
DAC
Value
10
1
1
7
8
1