AN1176 STMicroelectronics, AN1176 Datasheet - Page 7

no-image

AN1176

Manufacturer Part Number
AN1176
Description
68HC11/PSD813F1 DESIGN GUIDE
Manufacturer
STMicroelectronics
Datasheet
Notice that the memory map is basically divided into two areas. The upper memory (8000h to
FFFFh) is a common area, meaning the MCU will have access to this region regardless of what
memory page is active. This common area holds the:
Page
The lower half of memory (0000h to 7FFFh) is the region that will be “paged” or “banked”.
This paged area of 32K bytes allows the 68HC11 to address large amounts of memory (well
beyond the 64K byte limit of the 68HC11). We’ll place all 128K bytes of PSD main flash
memory across four 32K-byte pages (memory pages 0 through 3). The remaining half of the
PSD EEPROM will be placed on memory page 4 and used for general data.
5
68HC11 reset vector and initialization routines
68HC11 interrupt vectors and service routines
I/O management
Memory page management
SRAM variables and SRAM stack
Anything else that must be accessible no matter what memory page is selected.
(a n y p a g e )
C O M M O N
R E G IO N
R E G IO N
P A G E D
Figure 4 – Memory Map, Simple 68HC11/PSD813F1 design
F F F F
C 0 0 0
8 B 0 0
8 A 0 0
8 2 0 0
8 0 0 0
4 0 0 0
0 0 0 0
CSIO P, P S D C on tro l
68HC11 Regs/RAM
2 K b y tes S R A M
SY STEM
EES1
E E P R O M
EES0
E E P R O M
1 6K by te s
1 6K by te s
8 K b y tes
8 K b y tes
FS1
FS0
0 0 0 0
RS O
F la s h
F la s h
I/O
P A G E 0
0 0 0 0
1 6K by te s
1 6K by te s
FS3
FS2
F la s h
F la s h
6 8 H C 1 1 b o o ts fro m th e re se t
P A G E 1
8 0 0 0
ve c to r s to re d h e re
0 0 0 0
1 6K by te s
1 6K by te s
FS5
FS4
F la s h
F la s h
P A G E 2
8 0 0 0
0 0 0 0
1 6K by te s
1 6K by te s
FS7
FS6
F la s h
F la s h
P A G E 3
8 0 0 0
EES3
EES2
E E P R O M
E E P R O M
8 K b y tes
8 K b y tes
P A G E 4
4 0 0 0

Related parts for AN1176